Wafer Preparation 2t3w2n

VLSI Technology (Crystal Growth) Wafer Preparation CRYSTAL GROWTH

SHAPING (Grinding, Cutting)

ETCHING

POLISHING

The preparation of Silicon wafer from Silicon ingots required nominally six machining operations, two chemical operations and one or two polishing operation.

Shaping Operations:The different steps of Silicon shaping are as follows: (i) (ii) (iii) (iv) (v)

Removal of seed and tang ends Surface/diameter grinding Developing flats Slicing Shaping by edge contouring

In the first step of shaping operation seed and tang ends of the ingot is removed. The portions of the ingot that fail the resistivity and perfection evaluation are also cut away. The cuttings are sufficiently pure to be recycled after cleaning in the growing operation. The cutting is done by a circular saw. The second step of shaping is surface grinding. It is the step that defines the diameter of the material. Silicon ingots are grown slightly oversized because the automatic diameter control in crystal growing cannot maintain the needed diameter tolerance and crystal cannot be grown perfectly round. The tool that is used for grinding is shown below:

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VLSI Technology (Crystal Growth)

After grinding, one or more flats are ground along the length of the ingot. Basically, two flats are developed- “major or primary” flat and “secondary flat”. Primary flat: The largest flat is called as major or primary flat. This flat is used as a mechanical locator in the automated processing equipment to position the wafer and also serves to orient the IC device relative to the crystal. Secondary flat: The smaller flats are called secondary flats and serve to identify the orientation and conductivity type of material. They also provide a means of quickly sorting and identifying wafers should mixing occur. The below figures show the primary and secondary flats on the wafer.

After performing the above operation, the ingot is ready to be sliced into wafers. Slicing determines the four wafer parameters: 2|Prepared by Vimal Kant Pandey

VLSI Technology (Crystal Growth) (i) (ii) (iii) (iv)

Surface orientation Thickness Taper Bow

The surface orientation is measured by an X-ray method. Wafers of <100> orientation are usually cut “on orientation” and <111> is usually cut “off orientation” (by about 30) as required for epitaxial process. The thickness of wafer is essentially fixed by slicing although the final value depends on the subsequent operations. Thicker wafers are better able to withstand the stress of subsequent thermal process (epitaxy, oxidation, diffusion). Inner diameter slicing is the most common mode of slicing. The schematic of ID slicing process is shown below:

The ingot is prepared for slicing by mounting it in wax or epoxy on and then positioning the on the saw. This process has some limitations which are given below: (i) (ii) (iii)

Approximately one-third of the crystal is lost as sawdust It is very slow process; cutting speeds are nominally 0.05 cm/s. Another limit is the drum’s finite depth, which limits the length of the ingot section that can be cut into wafers.

Lapping: The wafer as cut varies enough in thickness to warrant an additional operation if the wafers are intended for VLSI application. A mechanical two-sided lapping operation, performed under pressure using a mixture of Al2O3 and glycerine, produces a wafer with flatness uniform to within 2um. This process helps ensure that surface flatness requirements for photolithography can be achieved in subsequent polishing steps. The final step in shaping is edge contouring, where a radius is ground on the rim of the wafer. Edge rounded wafers develop fewer edge chips during device fabrication and aid in controlling the buildup of photoresist at the wafer edge.

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VLSI Technology (Crystal Growth)

ETCHING After performing machining operations the surface and edge of the wafer get damaged and contaminated. The damaged and contaminated regions are on the order of 10um deep and can be removed by chemical etching. Depending on the solution used for etching, it is of two types: Acid etching and Alkali etching In acid etching, mixture of hydrofluoric, nitric and acetic acids have been used and alkali etching uses potassium or sodium hydroxide. The etching involves oxidation-reduction processes followed by dissolution of an oxidation product. In the hydrofluoric, nitric and acetic acid etching system nitric acid is the oxidant and hydrofluoric acid dissolves the oxidized products according to the following reaction: 3Si + 4HNO3 +18HF  3H2SiF6 + 4NO + 8H2O Acetic acid dilutes the system so that etching can be controlled. Water can also be used but acetic acid is preferable because water is a by-product of the reaction. The etching can be isotropic or anisotropic, according to the acid mixture or temperature. In HF-rich solutions, the reaction is limited by the oxidation step. This regime of etching is anisotropic and the oxidation reaction is sensitive to doping, orientation and defect structure of crystal. The use of HNO3-rich mixtures produces a condition of isotropic etching and the dissolution process then rate limiting. Over the range of 30 to 500C, the etching kinetics of an HNO3 rich solution have been found to be diffusion controlled rather than reaction limited. Thus transport of reactant products to the wafer surface across a stagnant boundary layer is the controlling mechanism and hence the HNO3-rich solutions are preferred for removing damage. A common etch formulation is a 4:1:3 mixture of HNO3 (79% by weight), HF (49% by weight) and CH3OOH acids. Alkaline etching: The dimensional uniformity introduced by lapping step is not maintained across the larger diameter wafers (>75mm) to a degree compatible with maintaining surface 4|Prepared by Vimal Kant Pandey

VLSI Technology (Crystal Growth) flatness in polishing. The hydrodynamics of rotating a large diameter wafer in solution do not allow for a uniform boundary layer, so a taper is introduced into the wafer. Projection lithography places demands on surface flatness that necessitate the use of alkaline etching. Alkaline etching is by nature anisotropic; thus etch rate depends on surface orientation. The reaction is generally reaction rate limited and wafers do not have to be rotated in the solution. Since boundary layer transport is not a factor, excellent uniformity can be achieved. Drawbacks of etching: An occasional problem with the damage removal process is insufficient etching which can lead to the generation of dislocations in subsequent treatments because of residual damage. Residual damage can be evaluated by measuring the fracture strength of the material after etching or by thermal wave mapping. Polishing: It is the final step of wafer preparation and its purpose is to provide a smooth, specular surface on which device features can be photoengraved. The process used for polishing is called Chemical Mechanical Polishing (CMP). The below figure show the polishing machine and a schematic of process.

The CMP process involves a polishing pad made of artificial fabric such as polyester felt, polyurethane laminate. Wafers are mounted on a fixture, pressed against the pad (which is both chemical and mechanical process). The porosity of the pad is a factor in carrying slurry to the wafer for polishing. The slurry is a colloidal suspension of fine SiO2 particles (100 A0 diameters) in an aqueous solution of sodium hydroxide. Under the heat generated by the friction, the sodium hydroxide oxidizes the Silicon with the OH- radical. This is the chemical step. In mechanical step, the Silica particles in the slurry abrade the oxidized Silicon away. Polishing rate and surface finish are complex functions of pressure, pad properties; rotation speed, slurry composition and pH of the polishing solution. Typical process removes 25um of Silicon. After polishing wafers are chemically cleaned with acid, base, and/or solvent mixtures to remove slurry residue and readied for inspection. Polished wafers are subjected to a number of measurements that are concerned with cosmetic, crystal perfection mechanical and electrical attributes.

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