Plc 5x2p29

LOGIC and the SIEMENS S7-200 PLC Ali Kazerani

© Ali Kazerani, 2006

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1. Summary of Logic 1.1 Bits and Logic A bit, or binary digit, is the smallest unit of data storage in a computer’s U and memory. Any bit can have one of two possible values: 1 (on, or true) and 0 (off, or false), corresponding to the two possible states of the “electronic switches” in the computer. Logic gates are electronic devices that take one or more bits as inputs and yield one bit as output, where the output relies upon the inputs in ways specific to the gates. Boolean variables are used to represent the values of individual bits, and Boolean algebra involves the representation and manipulation of these variables in ways that can be represented by logic gate-based circuits. 1.2 The NOT Gate Function:

Symbol:

Equation: Truth Table:

The simplest logic gate, the NOT gate, or inverter, is the only gate with only one input. The NOT gate outputs 1 when its input is 0 and outputs 0 when its input is 1. The output is said to be the complement of the input. A NOT gate with input A and output Y is shown as:

The Boolean equation for the operation of this gate is: Y=A NOT Gate A 0 1

Y 1 0

1.3 The AND Gate Function: Symbol:

Equation:

An AND gate may have two or more inputs. An AND gate outputs 1 if and only if both inputs are 1. A AND gate with two inputs A and B, and output Y is shown as:

The Boolean equation for the operation of this gate is: Y = A• B

2 Truth Table:

AND Gate A 0 0 1 1

B 0 1 0 1

Y 0 0 0 1

1.4 The NAND Gate Function:

Symbol:

The NAND (NOT AND) gate behaves in the same way as an AND gate whose output is inverted (that is to say, an AND gate followed by a NOT gate). A NAND gate outputs 0 if and only if both inputs are 1. A NAND gate with two inputs A and B, and output Y is shown as:

which, as discussed, is essentially

Equation: Truth Table:

The Boolean equation for the operation of this gate is: Y = A• B NAND Gate A 0 0 1 1

B 0 1 0 1

Y 1 1 1 0

1.5 The OR Gate Function: Symbol:

Like an AND gate, an OR gate may have two or more inputs. An OR gate outputs 1 if and only if at least one input is 1. An OR gate with two inputs A and B, and output Y is shown as:

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Equation: Truth Table:

The Boolean equation for the operation of this gate is: Y = A+ B OR Gate A 0 0 1 1

B 0 1 0 1

Y 0 1 1 1

1.6 The NOR Gate Function:

Symbol:

The NOR (NOT OR) gate behaves in the same way as an OR gate whose output is inverted (that is to say, an OR gate followed by a NOT gate). A NOR gate outputs 1 if and only if both inputs are 0. A NOR gate with two inputs A and B, and output Y is shown as:

which, as discussed, is essentially

Equation: Truth Table:

The Boolean equation for the operation of this gate is: Y = A+ B NOR Gate A 0 0 1 1

1.7 The XOR Gate

B 0 1 0 1

Y 1 0 0 0

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Function:

Symbol:

Equation:

Truth Table:

The XOR (eXclusive OR) gate is nearly identical to an OR gate with the same number of inputs. The only difference arises when A=B=1. In this case, an OR gate outputs 1 but an XOR gate outputs 0. An XOR gate outputs 1 if and only if exactly one of the inputs is 1. An XOR gate with two inputs A and B, and output Y is shown as:

The Boolean equation for the operation of this gate is: Y = A⊕ B As we will investigate later, this statement is equivalent to: Y = A• B + A• B XOR Gate A 0 0 1 1

B 0 1 0 1

Y 0 1 1 0

1.8 Algebraic Manipulation1 It is often useful to write a Boolean algebraic equation to represent an arrangement of logic gates, and then to simplify the equation either to create a truth table more easily or to design a simpler arrangement that requires the use of fewer gates and yet serves the same function. Many laws of base-10 algebra also apply to Boolean simplification, but in slightly modified forms, notably the commutative and distributive properties: i)

The commutative property for the AND operation: A• B = B • A ii) The commutative property for the OR operation: A+ B = B + A iii) The distributive property for the AND operation: ( A + B) • (C + D) = A • C + A • D + B • C + B • D iv) The distributive property for the OR operation: ( A • B ) + (C • D) = ( A + C ) • ( A + D) • ( B + C ) • ( B + D)

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Many of the laws that appear in this section were based on Bolton, W. Mechatronics: Electronic Control Systems in Mechanical Engineering, Second Edition. New York: Addison Wesley Zongner Publishing, 1999.

5 Often, considering the definitions of the operations themselves is useful in simplifying certain Boolean equations. Some of the rules that follow directly from the definitions are: v) vi) vii) viii) ix) x) xi) xii)

A• A = 0 A+ A =1 A•0 = 0 A+0 = A A •1 = A A +1 = 1 A• A = A A+ A = A

Since either A or its complement must be 0. Since either A or its complement must be 1. Since both “inputs” are not 1 (one of them is 0).

Since at least one of the “inputs” is 1.

Two additional laws are particularly useful in Boolean algebraic manipulation – the De Morgan laws: xiii) The De Morgan law for the complement of AND: A• B = A+ B xiv) The De Morgan law for the complement of OR: A + B = A• B 1.9 Solved Problems

1.9.1 Construct a truth table for this setup:

Solution:

Label gate outputs P1, P2, P3, and P4, as shown:

6 Construct truth table:

A 0 0 0 0 1 1 1 1

Inputs B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

P1 1 1 1 1 1 1 1 0

Intermediate P2 P3 1 1 0 0 1 1 0 1 1 1 0 0 1 1 0 1

1.9.2 Write a Boolean equation for this setup, then simplify:

Solution:

Label gate outputs P1 and P2, as shown:

P1 = A ⊕ B P2 = A • B Y=P1+P2

(1) (2) (3)

Start with (3): Y=P1+P2 Substitute P1, P2 from (1), (2): Y = ( A ⊕ B) + ( A • B)

= ( A • B + A • B) + ( A • B) = A• B + A• B • A• B = A • B • A • B • ( A + B)

P4 0 0 0 0 0 0 0 0

Output Y 1 0 1 0 1 0 1 0

7 = ( A + B) • ( A + B) • ( A + B)

= ( A + B) • ( A + B) • ( A + B)

= ( A • A + A • B + A • B + B • B) • ( A + B) = (0 + A • B + A • B + 0) • ( A + B) = ( A • B + A • B) • ( A + B)

= A• A• B + A• A• B + A• B • B + A• B • B = 0• B + A• B + A• 0 + A• B = A• B + A• B = A• B = A+ B 1.9.3 Simplify and construct a truth table: Y = A+ B +C + A+ B Solution: Y = A+ B +C + A+ B = A• B + C + A• B = A • ( B + C + A) • B = A• B • B + A• B •C + A• A• B = A•0 + A+ B + C + 0• B = A+ B +C

Construct truth table:

A 0 0 0 0 1 1 1 1

Inputs B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

Intermediate A+B+C 0 1 1 1 1 1 1 1

Output Y 1 0 0 0 0 0 0 0

8 1.10 Supplementary Problems

1.10.1 Simplify and create a truth table for each of the following: a) ( A + B) • ( A + B) b) A + B • ( A • B + C ) c) A ⊕ B + A • B + B 1.10.2 For how many different inputs (P,Q,R,S) does the system

have output Y=1? 1.10.3 Using a truth table (with intermediate values), prove the identity A ⊕ B = A • B + A • B , for Boolean variables A and B. 1.10.4 It is sometimes useful to be able to simulate the operation of an XOR gate using some arrangement of the other five logic gates. One such arrangement is:

Algebraically, prove that the above setup does indeed emulate an XOR gate. Make use of the identity A ⊕ B = A • B + A • B .

9 1.10.5 Prove the two De Morgan laws using a truth table for each. 1.11 Solutions to Supplementary Problems

1.11.1 a) ( A + B) • ( A + B)

= A• A + A• B + A• B + B • B = 0 + A• B + A• B + B = B • ( A + A + 1) = B •1 =B b) A + B • ( A • B + C )

= A + B • ( A • B • C) = A + B • A• B •C

= A + ( B • B) • A • C = A + 0• A•C =A =A c) A ⊕ B + A • B + B = A• B + A• B + A• B • B = A • B • A • B + ( A + B) • B = ( A + B) • ( A + B) + A • B + B •B = ( A + B) • ( A + B) + A • B + 0

= A• A + A• B + A• B + B • B + A• B = 0 + A• B + A• B + 0 + A• B = A • B + A • ( B + B) = A • B + A •1 = A• B + A

10 1.11.2 Label gate outputs A1 and A2, as shown:

From the diagram, A1 = P + Q

(1)

A2 = A1 + R + S (2) Y = A2 + Q + R (3) Start with (3): Y = A2 + Q + R Substituting in the expression for A2, from (2),

Y = A1 + R + S + Q + R Substituting in the expression for A1, from (1), Y = P+Q+ R+ S +Q+ R = P +Q + R + S •Q• R

= (P + Q + R + S ) • Q • R = (P • Q + R + S ) • Q • R = P •Q•Q• R + R•Q• R + S •Q• R = P • Q • R + ( R • R) • Q + S • Q • R = P•Q• R + 0•Q + S •Q• R = P•Q• R + 0+ S •Q• R = P •Q• R + S •Q• R = (P + S ) • Q • R Set Y=1: 1 = (P + S ) • Q • R ∴ Q =1

(4)

∴ R =1 (5) ∴ P + S =1 (6) (4) and (5) give Q = R = 0.

11 (6) implies ( P, S ) ∈ {(0, 0), (1,1), (0,1)} ∴ ( P, Q, R, S ) ∈ {(0, 0, 0, 0), (1, 0, 0,1), (0, 0, 0,1)}

Therefore 3 different inputs (P, Q, R, S) yield Y=1. 1.11.3 Inputs A B 0 0 0 1 1 0 1 1

Left Side A⊕ B 0 1 1 0

A 1 1 0 0

B 1 0 1 0

Right Side A• B A• B 0 0 1 0 0 1 0 0

A• B + A• B 0 1 1 0

Since the left side equals the right side in every case, therefore the identity is established. QED. 1.11.4 Label gate outputs P1, P2, P3, as shown:

From the diagram, P1 = A • B (1) P 2 = A • P1 (2) P3 = B • P1 (3) Y = P 2 • P3 (4) Start with (4): Y = P 2 • P3 Substituting in the expression for P3, from (3), Y = P 2 • B • P1 Substituting in the expression for P2, from (2), Y = A • P1 • B • P1 Substituting in the expression for P1, from (1), Y = A• A• B • B • A• B

12 = A• A• B + B • A• B = ( A • A • B) + ( B • A • B)

(

)

(

)

= ⎡ A • A + B ⎤ + ⎡B • A + B ⎤ ⎣ ⎦ ⎣ ⎦

(

)

= A + B • ( A + B) = A• A + A• B + B • A+ B • B = 0 + A• B + B • A+ 0 = A• B + B • A = A⊕ B (Q A ⊕ B = A • B + A • B ) As required. Therefore the setup does indeed emulate an XOR gate. QED. 1.11.5 First, prove A • B = A + B , as follows: Inputs A 0 0 1 1

B 0 1 0 1

Left Side A• B A• B 0 1 0 1 0 1 1 0

A 1 1 0 0

Right Side B 1 0 1 0

A+ B 1 1 1 0

Since the left side equals the right side in every case, therefore the identity is established. QED. Now, prove A + B = A • B , as follows: Inputs A 0 0 1 1

B 0 1 0 1

Left Side A+ B A+ B 0 1 1 0 1 0 1 0

A 1 1 0 0

Right Side B 1 0 1 0

A• B 1 0 0 0

Since the left side equals the right side in every case, therefore the identity is established. QED.

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2. Programming the Siemens S7-200 PLC 2.1 Introduction to the S7-200: Scan Cycle and Stack

The Siemens S7-200 PLC (Programmable Logic Controller) does more than simply run the programs ed to it. It is designed to repetitively execute a series of tasks. One repetition of these tasks is called a scan cycle. The tasks that must be executed, and the order in which these must be done, are as follows:

The contents of the the Process-Image Output are read and written to the

The physical inputs of the PLC are read and written to the Process-

Image Input .

physical outputs.

The PLC executes the program from the first instruction to the END instruction.

The PLC’s U checks the program memory, firmware, and I/O modules.

Messages sent to the PLC communications port are processed.

The PLC has two modes of operation, RUN and STOP. IN RUN mode, all components of the scan cycle are executed. In STOP mode, the program on the PLC is not executed and the self-test diagnostics are not executed. Special program components called interrupt routines are stored as part of the program, but are executed at any time during the cycle when the interrupt events occur, whether during the program execution stage or not. The logic that controls the U is stored in a special memory area: the stack. The stack is essentially an array of nine bits (it has nine levels, numbered from 0 to 8):

The logical operations we will discuss all involve writing to, reading from, and manipulating the stack, particularly the bit in level 0. 2.2 Accessing Memory and Symbolic Addressing

The memory of the PLC is divided into a number of memory areas, each of which is represented by a different letter identifier. For example, • The Process-Image Input is represented by the identifier I. At the beginning of each scan cycle, the U reads the states (1 or 0) of the physical inputs to the PLC and writes them into this . • The Process-Image Output is represented by the identifier Q. At the end of each scan cycle, the U writes the states of this to the physical outputs of the PLC.

14 •

The Variable Memory Area is represented by the identifier V. Intermediate values resulting from the operations carried out in the program may be stored here to be used later in the program. The process-image s are usually read from when a PLC program relies upon the states of the physical inputs and outputs in order to be executed successfully. However, the immediate states of the I/O bits (i.e. not those read in at the top of the scan cycle, but rather during the program’s execution) can also be accessed, but this is a much slower process than simply using the I and O s. To access the value of an individual bit, byte.bit addressing is used. A byte is a series of 8 bits. Each memory area is made up of a number of these bytes, each in turn consisting of 8 bits. The syntax for addressing a certain bit in memory is: [memory_area_identifier][byte_address].[bit_number] For instance, to access the fifth bit in the first byte of the input , the address is I0.4. Notice that the byte_address is 0, not 1, because bits and bytes are numbered starting from 0. The bit_ number is 4, not 5, for the same reason. In order to make a PLC program’s code more readable, symbolic addressing is often used. Instead of accessing bits by their byte.bit addresses, symbolic names, or symbols, are used. For example, if the I0.0 bit represents the state of an on/off switch, that bit may be given the symbol switch_on_off, and if the Q0.5 bit output will operate a fan motor, then its symbol might be motor_fan. Symbols chosen by the are written in the Symbol Table. 2.3 LAD and STL

There are two editors that may be used to create the code for a PLC program – the ladder (LAD) editor and the statement list (STL) editor. These two editors will be the focus of sections 2.4 and 2.5. 2.4 The Ladder Editor

The LAD editor graphical. That is to say, in the LAD editor, an arrangement of labelled symbols is used to represent the program code. There are three basic symbols that are used: • s, which are used to represent logical input conditions (corresponding to switches, pushbuttons, etc.), • coils, which are used to represent logical output conditions (corresponding to motors, lights, relays, etc.), and • boxes, which are used to represent additional instructions (such as subroutines, math functions, timers, and counters). Programs written in the LAD editor are divided into a number of “Networks”, which may be compared to rungs of a ladder. In each scan cycle, the U first carries out the operations in the first network, then those in the second, and so on until the end of the program. Each network is “read” from left to right. LAD programs simulate power flow from a source on the left side of the window, through a series of input conditions (s that are either on or off), which then enable one or more output conditions (coils). Note that if the power flow is ever stopped within a network before reaching a

15 coil, power would not flow to the coil and its logical state would be 0 (off). Power flow could be stopped by a normally-open being open or a normally-closed being closed. The LAD editor is used worldwide. Its simple graphical approach and structure are very appealing. However, some programs may be very difficult or even impossible to create in LAD and must be done in STL. Note that not all STL programs can be changed to LAD simply by switching editors after the code is written in STL. LAD programs, however, can always be changed to STL after the code is even partly written. This is because LAD is simpler and more limited than STL since STL language is very close to the language of the U itself, while the graphics of LAD are not. 2.5 The STL editor

The STL editor is textual. Programs written in STL consist of a number of lines of code, each consisting of one or two components. The component that must be present in every line of code is the instruction mnemonic. These mnemonics form the basis of STL, since the U uses the mnemonics alone to determine the operation that is to be carried out, such as the AND, OR, and NOT operations. But what is an instruction mnemonic? It is an abbreviated from of an instruction. Each instruction in STL identifies an operation to be carried out by the U. The second component that may or may not be present following the mnemonic is the operand or operands. The operand identifies the bit or byte to which the mnemonic refers. 2.6 A Simple PLC Program

Quite a few of the most fundamental mnemonics and symbols can be demonstrated in a single program, in either LAD or STL. We will discuss both. 2.6.1

Loading

Function:

In order for the value of any bit to be used “by itself” in a program, that bit must first be loaded onto the stack. This bit is written to the top level of the stack, all other stack bits are pushed down one level, and the bottom bit is lost.

Stack Diagram:

Where iv0 through iv8 are the initial stack bit values, and [bit] is the newly loaded bit.

Syntax:

STL LD [bit], to load the value of

LAD If [bit] is normally off, a (-| |-)

16 [bit] onto the top of the stack. (Used when [bit] is normally off.)

must be created next to the vertical line at the left of the window.

LDN [bit], to load the complement of [bit] onto the top of the stack. (Used when [bit] If the bit is normally on, use the is normally on.) normally closed , -| / |-,

2.6.2

ANDing

Function:

The AND instruction “AND”s a bit with the bit stored at the top of the control stack. That is to say, if the bit at the top of the stack is S0, then calling the AND instruction with operand [bit] replaces S0 with S 0 • [bit ] .

Stack Diagram:

S 0 • [bit ]

Syntax:

STL A [bit], to AND the value of [bit] with the bit at the top of the stack. AN [bit], to AND the complement of [bit] with the bit at the top of the stack.

LAD If [bit] is normally off, a (-| |-) must be created in series with the preceding , so power only flows through if all s are on. other s

If the bit is normally on, use the normally closed , -| / |-,

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other s

2.6.3

ORing

Function:

The OR instruction “OR”s a bit with the bit stored at the top of the control stack. That is to say, if the bit at the top of the stack is S0, then calling the OR instruction with operand [bit] replaces S0 with S 0 + [bit ] .

Stack Diagram: S 0 + [bit ]

Syntax:

STL O [bit], to OR the value of [bit] with the bit at the top of the stack. ON [bit], to OR the complement of [bit] with the bit at the top of the stack.

LAD If [bit] is normally off, a (-| |-) must be created in parallel with the other s, so power flows through when any s are on.

other s

If the bit is normally on, use the normally closed , -| / |-,

2.6.4

NOTing

Function:

The NOT instruction “NOT”s the bit stored at the top of the control stack. That is to say it replaces the top bit with its own complement.

18 Stack Diagram:

S0

STL Syntax:

NOT

(Note: NOT is one of very few instructions that have no operands in STL.)

2.6.5

Setting and Resetting

Function:

Syntax:

2.6.6

LAD A NOT (-|NOT|-) must be created in series with the preceding s, so that if power is flowing, it is stopped, and if no power is flowing, the NOT supplies power flow.

Setting a bit will change its state to 1. Resetting will change a bit’s state to 0. STL LAD S [bit], 1, sets the value of To set the value of [bit] to 1, [bit] to 1. an S-coil ( -(S)- )must be placed in series with the rest R [bit], 1, resets the value of the network. of [bit] to 0. To reset the value of [bit] to 0, an R-coil ( -(R)- ) must be placed in series with the rest of the network.

Asg

Function:

Syntax:

Asg a value to a bit involves changing its state to that value. The value assigned is always equal to that of the bit at the top of the control stack. STL LAD To assign the value of the top = [bit] stack bit to [bit], a coil ( -( )- ) must be placed in series with the rest of the network, and labelled with [bit].

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2.6.7

Commenting

Function:

Syntax:

2.6.8

Comments are fragments of code that are not read by the computer. In a comment, a programmer may be able to state the purpose of a line of code, explain variables, etc. Commenting makes code more readable. STL LAD // [comment], on a line by Networks can be titled and itself or to the right of a commented by double-clicking line of code on the line that specifies the network number, and then typing in the required information in the dialog.

Putting it all Together

Here, we will create our first program. The requirements for this program are: 1. It must read in the values of I0.0 and I0.1. If I0.0 is on, but I0.1 is not, then turn Q0.4 on. Otherwise, turn it off. 2. If either I0.2 or I0.3 is on, then turn Q0.5 on. Otherwise, turn it off. 3. If I0.4 is pressed, then turn Q0.6 on. It must then stay on until I0.5 is pressed.

We will first construct our program in LAD. 1. Open the programming software, Simatic’s STEP 7-Micro/WIN 32. The default editor is LAD. 2. Just under Network 1 in the SIMATIC LAD window, there is an arrow. This is where we must begin assembling the elements of the network. Network 1 will be used to satisfy requirement 1. So, we must first get the value of I0.0. 3. Create a on the arrow by pressing F4. Then choose the topmost option (-| |-). Label the I0.0 by clicking where ??.? appears in red above the , and typing in I0.0. Power flows through the iff I0.0 is on. 4. Click on the arrowhead to the right of the , then repeat step 3, but this time choose the second option (-| / |-), and label it as I0.1 instead of I0.0. If there is power flow into this , then power flows out iff I0.1 is off. At this point, power is still flowing iff I0.0 is on and I0.1 is off. 5. Power is flowing as desired. The network must end in Q0.4, according to the instructions, so click on the arrowhead and press F6 to create a coil. Then label it as Q0.4. Requirement #1 is now satisfied.

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6. Network 2 will be devoted to fulfilling requirement #2. Therefore, the value of I0.2 must first be read in. So, create a (F4) on the arrowhead in Network 2, and label it as I0.2. 7. Power must flow to Q0.5 iff either I0.2 or I0.3 is on. Therefore another must be created for I0.3, and placed in parallel with the other . This can be done by clicking on the first , right-clicking, then selecting Insert > Vertical. Do not click on the arrowhead. To create the , press F4; label it as I0.3. 8. Power is now flowing iff either I0.2 or I0.3 is on, as required. Now, create a coil on the arrowhead (click, then F6), and label it as Q0.5.

9. Networks 3 and 4 will be devoted to fulfilling requirement #3. Therefore, the value of I0.4 must first be read in. So, create a (F4) on the arrowhead in Network 3, and label it as I0.4. 10. Power is now flowing iff I0.4 is on. If this is the case, Q0.6 is to turn on and stay on. To do this, its value must be set to on. Thus, click the arrowhead, create a coil (F6), and select the option S. Label it with Q0.6 on top, and 1 on bottom. 11. Q0.6 must now be turned off if I0.5 is pressed. That is to say, it must be reset if I0.5 is on. Thus, create a on the arrowhead in Network 4, and label it as I0.5. 12. If power is flowing, Q0.6 must be reset, so create a coil on the arrowhead, and select the option R. Label it with Q0.6 on top, and 1 on bottom.

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At this point, it is important to realize that two networks had to be used for requirement #3 because no more elements can be put in Network 3 following the Scoil, or any coil for that matter, so a new Network was started. This is not the case in STL. In a single network, setting, resetting, and asg do not require that the network be terminated. 13. All three requirements are now satisfied. To save the program, select Save As… from the File menu, and name the program appropriately. 14. To to the PLC, set the PLC to STOP mode from the Standard Toolbar at the top of the screen, , then click the button, . 15. Press Enter for all dialogs that appear. When the Successful dialog appears, set the PLC to RUN mode by clicking program in STL, select STL from the View menu.

. That’s it! To see the

We will now construct our program in STL. For clarity, we comment every line of code. 1. Open the programming software, Simatic’s STEP 7-Micro/WIN 32. The default editor is LAD. To enter the STL editor, select STL from the View menu. 2. Delete all the code in the SIMATIC LAD code editor window and type in NETWORK 1 // Satisfies requirement 1. 3. Network 1 will be used to satisfy requirement 1. So, we must first get the value of I0.0. That is, we must load I0.0 to the top of the stack. Thus type LD I0.0 // If I0.0 is on… 4. We want the top stack bit to be on iff I0.0 is on and I0.1 is not. So we want the top stack bit to be equal to itself ANDed with the complement of I0.1: AN I0.1 // but I0.1 is not, 5. At this point, the top stack bit is on iff I0.0 is on and I0.1 is not, as desired. The top stack bit now needs to be written to Q0.4. Therefore, type: = Q0.4 // then turn Q0.4 on. 6. Network 2 will be used to satisfy requirement 2. We want Q0.5 to turn on if either I0.2 or I0.3 is on, so the top stack bit should be given the value of I0.2 ORed with I0.3. So we will first load I0.2 to the top stack bit, then OR the top stack bit with I0.3, then assign the new top bit value to Q0.5. Type in: NETWORK 2 // Satisfies requirement 2. LD I0.2 // If either I0.2, O I0.3 // or I0.3 is on,

22 = Q0.5 // then turn Q0.5 on. 7. Network 3 will be used to satisfy requirement 3. Since Q0.6 must be turned on and left on iff I0.4 is turned on, therefore we must load I0.4 onto the top of the stack, setting Q0.6 to 1 if the top stack bit is on. To do this, type: NETWORK 3 // Satisfies requirement 3. LD I0.4 // If I0.4 is on, S Q0.6, 1 // then turn Q0.6 on and leave it on. 8. Now, since Q0.6 must be turned off and left on iff I0.5 is turned on, therefore we must load I0.4 onto the top of the stack, resetting Q0.6 if the top stack bit is on. To do this, type: LD I0.5 // If I0.5 is on, R Q0.6, 1 // then turn Q0.6 off.

9. All three requirements are now satisfied. To save the program, select Save As… from the File menu, and name the program appropriately. 10. To to the PLC, set the PLC to STOP mode from the Standard Toolbar at the top of the screen, , then click the button, . 11. Press Enter for all dialogs that appear. When the Successful dialog appears, set the PLC to RUN mode by clicking LAD, select LAD from the View menu.

. That’s it! To see the program in

2.7 Solved Problem

2.7.1 Create a program to simulate a NAND gate, with inputs A, B, and output Y. Solution: Recall that a NAND gate is equivalent to an AND gate followed by a NOT gate, in series. The symbol table is as follows:

The program may be as follows: In LAD:

23 In STL:

2.8 Unsolved Supplementary Problems

2.8.1 a) b) c)

Program the PLC to simulate each of the following: An AND gate, with inputs A and B, and output Y. An XOR gate, with inputs A and B, and output Y. A four-input NAND gate, with inputs A, B, C, D, and output Y.

2.8.2 A device called a half-adder may be used to add to bits together. The half adder that adds two bits, A and B, may be set up as follows:

Where X is the units digit of the sum and Y is the carry digit, which is analogous to the tens digit in decimal addition. Since there is no special instruction in the SIMATIC set (the instruction set we are using) for an XOR gate, the above setup may be replaced with

Create a program that simulates this half-adder.

24 2.8.3 Program the PLC to operate a robotic vehicle that is to find its way to the end of a maze, if there is one. As shown in fig. 1, the vehicle is equipped with three sets of sensors: • the left sensors detect the presence of a wall immediately to the left of the vehicle supply power to sensor_L if a wall is detected, • the right sensors detect the presence of a wall immediately to the right and supply power to sensor_R if a wall is detected, • the front sensors detect the presence of a wall immediately in front and supply power to sensor_F if a wall is detected, to sensor_red if a red-colored wall is detected, and/or to sensor_green if a green-colored wall is detected. The vehicle is powered forward by a motor that operates only as long as power is supplied to the motor_main relay. To turn to the left, the main motor must stop, and a separate motor turns the vehicle to the left. The motor operates only as long as there is power flow to motor_left. Similarly, the vehicle rotates to the right as long as there is power to motor_right. It takes 3.0 s for the vehicle to rotate completely to the left or completely to the right. Symbolic addressing should be as follows: Name sensor_L sensor_F sensor_R sensor_red sensor_green motor_main motor_left motor_right

Address I0.0 I0.1 I0.2 I0.4 I0.5 Q0.4 Q0.5 Q0.6

The vehicle is initially placed in the maze so that it is walled in on 3 sides – to its left, to its right, and behind. The wall behind the robot’s starting position is colored green. (See fig. 2.) The wall that marks the end of the maze is colored red. All other walls in the maze are colored black, and all are at right angles to each other. The robot and the program must stop iff the vehicle has either reached the end of the maze, or has reached the starting wall again, having made certain that there is no way to the end. Fig. 2: At the Start of the Maze

Fig. 1: The Robot Vehicle FRONT

front sensors

motion

REAR

left sensor

right sensor starting wall, colored green