Innovus Flow j5g18

set init_verilog set init_pwr_net {VDD} set init_gnd_net {VSS} set init_io_file set init_f_file set init_mmmc_file <mcmm.view>

#MCMM create_library_set –name Setup –timing {…} create_library_set –name Hold –timing {…} create_constraint_mode –name SDC –sdc_files {…} create_op_cond –name OPcond –library_file <.lib> -P {} –V{} –T{} create_rc_corner –name -cap_table <.CapTbl> -T {}

create_delay_corner –name DelayCorner –early_library_set {Setup} –rc_corner create_delay_corner –name DelayCorner - late_library_set {Hold} –rc_corner

create_analysis_view –name setup_view –constraint_mode {SDC} – delay_corner {DelayCorner} create_analysis_view –name hold_view –constraint_mode {SDC} – delay_corner {DelayCorner} set_analysis_view –setup {setup_view} –hold {hold_view}

#To create define top cell name set init_design_settop {1} set init_top_cell #Check Netlist Uniqueness while importing design set init_design_uniquify {1}

#To update existing lib files in design update_library_set –timing {…}

#Get Design Tech node getDesignMode -process #Sanity checks checkDesign |-netlist| |-physicalLibrary| |-timingLibrary| check_timing checkUnique timeDesign (similar to report_qor)

report_clocks

#ZIC check setDelayCalMode –ignoreNetLoad true #Change above command to false after timing check report_timing |timeDesign

#Check the views/scenarios all_analysis_views all_hold_analysis_views all_setup_analysis_views #Report all views in design report_analysis_views

#Set a view set_anaylsis_view –setup –hold

#Pin/Port Assignment loadIoFile ./ (or) assignIoPins #Add I/O Buffers attachIOBuffer –port –in -out -suffix “_buff” –markFixed addIoFiller –cell –prefix –side #Note: Before adding io fillers add the global net connection to apply rules for supply pins.

#Set Tech/Design Mode -> Specify process tech. node for design which changes the coupling capacitance 130nm -> 3 45nm and below -> 0.1 setDesignMode –process 45 setDesignMode –reset –process

#Do Floor Plan - Decide AR and IO Clearance Floorplan->Edit Floorplan->Color Module floorplan –site addIoFiller –cell -prefix –side #Apply blockages and halos addHaloToBlock {L B R T} –allBlock addRoutingHalo –all_blocks –space –bottom –top deleteHaloFromBlock –allBlock createPlaceBlockage –box –type soft deletePlaceBlockage -all #Mark steps during FP refineMacro –markStep refineMacro –restoreStep -1

#Remove Macros unplaceAllBlocks

#Post FP Check

checkDesign –all checkFPlan –reportUtil report_power report_constraint #Fix Macros setBlockPlacementStatus –allHardMacros –status fixed

#Save FP saveFPlan #Power Planning clearGlobalNets globalNetConnect VDD –type pgping –pin VDD –inst * globalNetConnect VSS –type pgping –pin VSS –inst * #Tie cells have to be tied to VDD and VSS globalNetConnect –type tieHigh –pin VDD –inst * globalNetConnect –type tielow –pin VSS –inst * # Common Power File (F)/UPF for MV design runCLP

#Add Ring if required, straps and power rails In Power tab

#Checks for Power Plan -> DRC, Connectivity & Geometry

#If scan chain is present in design

defIn - #Check Scanchains scanTrace setPlaceMode –place_global_ignore_scan true scanTrace –lockup [-verbose] setScanReorderMode -<switches…> #If data lockup latches are present #specifyScanChain specifyLockupElement #To perform SI analysis set OCV for delay calc. mode. This is required for noise analysis -> Done after PostRoute setAnalysisMode –analysisType onChipVariation –checkType {setup | hold} – aocv {true | false} #Optional – Place JTAG cells near core before doing placement specifyJtag –cell | inst jtag* placeJtag reportJtagInst unplaceJTAG #Set U cores setMultiuUsage –keepLicense true –localU 16 #Set DRV limits/Before setting this set MMCM constraint modes (set_interactive_constraint_modes) set_max_capacitance set_max_transition set_max_fanout reportFanoutViolation

#To create path groups group_path –name reg2reg –from all_s –to all_s reportPathGroupOptions resetPathGroupOptions #Set Optimization for diff. path groups setPathGroupOptions reg2reg –effortLevel high

#Pin Placement assignIoPins checkPinAssignment

#Placement/GigaPlace setPlaceMode –reset setPlaceMode –fp false setPlaceMode –place_global_cong_effort -noPrePlaceOpt –fixDrc place_global_timing_effort getPlaceMode -setupTargetSlack –fixDrc <switches…> placeDesign

#Method 2 (placeDesign + optDesign –preCTS) Provides better PPA and faster run time/GigaOpt setPlaceMode -<switches…> setOptMode -<switches…> #setOptMode contains options for all optDesign command used in design setOptMode –fixFanoutLoad –maxDensity –placeIoPins place_opt_design (placeDesign + optDesign –preCTS)

#Checks after Placement checkPlace checkFPlan –reportUtil reportCongestion reportArea report_timing timeDesign –numpaths 50 –preCTS –drvReports #to report DRVs and setup timeDesign –preCTS –hold –outDir #to report hold violations report_constraints -type report_constraints –all_violators

# Timing optimization on design and on reg2reg paths/ or other paths analyze_paths_by_basic_path_group #To automatically get basic path groups in Timing Debugging group_path –name -from -to setPathGroupOptions –targetSlack -100 –weight –effortLevel reportPathGroupOptions setOptMode –yieldEffort –effort –fixDRC –fixFanoutLoad –setupTargerSlack – holdTargetSlack -<switches…> optDesign –preCTS –setup –drv -<switches…> reset_path_group –all

#Add Repeaters ecoAddRepeater –net –cell BUFFx4 #If it’s a inverter, it has to be added in pairs ecoChangeCell –upsize –inst ecoAddRepeater –net –cell INVX4 (OR)

ecoAddRepeater –term –cell BUFFX4 ecoChangeCell –upsize –inst ecoRoute

#Remove Placement unplaceAllInsts

#(Setting Scenario & propagating CLK) View/Scenario & has to set before going to CTS all_analysis_views get_sdc_mode | all_constraint_modes update_constraint_mode –sdc_files set_interactive_constraint_modes <sdc_name> | set_interactive_constraint_modes [all_constraint_modes –active] #to set all constraint modes as active get_interactive_constraint_modes set_propagated_clock [all_clocks] get_propagated_clock –clock [all_clocks] #Check if clocks are propagated

#Check min clock pulse width report_constraints

#STA (Timing -> Debug Timing) timeDesign –preCTS –drvReports –outDir #To report DRVs & Setup timeDesign –preCTS –hold –outDir #To report hold violations report_timing –path_group reg2reg

#Move cells to reduce Congestion and type the foll. command to update Gcell Destiny Map reportDensityMap

#Pre CTS Fixes (to fix max tran, max cap and max fanout) setOptMode –fixFanoutLoad true optDesign –preCTS –drv -setup #optDesign command is used for Pre/Post CTS timing optimization

#Report QOR once again to check for DRVs timeDesign –preCTS -drvReports report_constraints –all_violators

#Creating NDR add_ndr –name –spacing {metal1:metal4 ….} |–width {metal1:metal4 …} | -generate_via exportNdr -def modifyNdr –name #List existing NDR dbGet head.rules.name #Adding NDR to route type create_route_type –name leaf_rule –non_default_rule 2W1S – top_preferred_layer –bottom_preferred_layer –shield_net VSS create_route_type –name trunk_rule –non_default_rule 2W2S – top_preferred_layer M1 botton_preferred_layer M4 –shield_net VSS set_ccopt_property –net_type trunk route_type trunk_rule set_ccopt_property -net_type leaf route_type leaf_rule

#Set CCOPT properties #Set NDR rules for CTS set_ccopt_property –net_type leaf/trunk/top -route_type leaf_rule/trunk_rule/top_rule set_ccopt_property buffer_cells {BUFx12…} set_ccopt_property inverter_cells {INV…} set_ccopt_property clock_gating_cells {ICG…} #Set target skew for whole design set_ccopt_property target_skew #Set target skew for particular skew group create_ccopt_skew_group -<switches…> set_ccopt_property –skew_group target_skew set_ccopt_property use_inverters –clock_tree true #Set preference for inverters Set_ccopt_property use_inverters true #Set target skew and max trans set_ccopt_property target_max_trans 100ps set_ccopt_property target_skew 50ps #Get applied CCOPT Properties get_ccopt_property –target_max_capacitance get_ccopt_property –target_max_trans #Reset all the properties set in set_ccopt_property reset_ccopt_config #Report special pins in CTS report_ccopt_clock_trees –list_special_cells

#Dumping out a SPEC file

create_ccopt_clock_tree_sepc –file

#Classical CTS #Apply settings for CTS setCTSMode setOptMode -<switches…> #Create SPEC file create_clockTreeSpec –file clockDesign –specfile -outDir clock_report ccopt_design –cts

#CCD CTS setDesignMode -<switches…> setOptMode -<switches…> #Create/Source SPEC file create_ccopt_clock_tree_spec –file source create_ccopt_clock_trees create_ccopt_clock –spine/HTree #Place high drive strength clk buffers near newly created stripes to reduce IR drop create_ccopt_preferred_cell_stripe –cells { } #To reduce EM Lets you find the maximum capacitance that a cell can drive without violating EM constraints and then set that cap value as the target max cap. value for that cell. set_ccopt_property consider_em_constraints rms|avg|peak

get_ccopt_property consider_em_constraints

#Remove –cts to perform CCD ccopt_design (optional->generally not required if u are using CCD) OptDesign –postCTS –hold

#Clock Tree Debugger ctd_win get_ctd_win_id –detail

#PostCTS checks timeDesign –postCTS -drv–outDir #Setup violations #Hold Checks setAnalysisMode –check_type hold timeDesign –postCTS –hold report_timing –check_type hold #Post CDDCTS checks report_ccopt_clock_tress –file clock_trees.rpt report_ccopt_skew_groups –file skew_groups.rpt report_clock_timing –type summary

#If there are high no. of HOLD violations PostCTS use “optDesign” command #Hold has to be reduced at postCTS, but does not have to be 0. setOptMode –holdTargetSlack -0.2 optDesign –postCTS –hold –outDir timeDesign –postCTS –hold –outDir #Check hold violations again

#Signal Routing #PreRoute Checks checkPlace Geometry add_tracks #Tracks are already added based on routing pitch, layer width, spacing and min via widths. It can be overwritten by using the above command. #To fix SI induced max trans. setOptMode –fixSISlew true #Set routing options (The options set using this command affects the following commands ->detailRoute, globalRoute, globalDetailRoute, routeDesign #To set Hard Layer Limits setNanoRouteMode –routeTopRoutingLayer –routeBottomRoutingLayer – routeWithTimingDriven –fixAntenna <-switches…> #To keep clock nets status fixed use setNanoRouteMode –routeDesignFixClocksNets true #To set Soft Layer Limits setAttribute -bottom_preferred_routing_layer -top_preferred_routing_layer -preferred_routing_layer_effort #Set max and min routing layer for EARLY GLOBAL ROUTE -> It affects placeDesign and optDesign setRouteMode –earlyGlobalMinRouteLayer –earlyGlobalMaxRouteLayer earlyGlobalRoute -> Quick global route for estimating congestion and parasitic RC values setRouteMode -reset

setNanoRouteMode –routeBottomRoutingLayer setNanoRouteMode –routeTopRoutingLayer setNanoRouteMode –reset

#Reducing CrossTalk setAttribute –preffered_extra_space #adds extra space between critical nets -weight # to give priority to critical nets within switch box -avoid_detour # to ensure the critical nets are routed as short as possible - Minimize long parallel wires -shield_net VSS

#Fix Antenna using Diodes setNanoRouteMode –routeInsertAntennaDiode true globalDetailRoute globalNetConnect

#Perform Routing/NanoRoute routeDesign –global routeDesign –detail Note: For detail routing. (Switch Boxes ->5x5 SB is 25 gcells). SWs grow bigger after each iteration (typical -> 20iterations). No improvement beyond 20 iterations. (OR) #Timing Driven (Run time and no. of violations increase, since detours are restricted for the most part; so increase congestions ) routeDesign –timingDriven –SI driven –globalDetail editDeleteViolations #if violations are there

Reroute the Design

#PostRoute Checks The analysis needs to be set to OCV in post route instead of BcWc. setAnalysisMode –analysisType onChipVariation Recommendation -> set –pr both #Remove CRPR for both setup and hold modes timeDesign –postRoute –drv –slackReport #setup timeDesign –postRoute –slackReport –hold checkRoute reportWire #includes net name, wire ratio (total net routing length/half – perimeter of net bounding box), real and min wire lengths, no. fo vias, fanins and fanouts reportRoute

#Post Route Optimization (If no. of violations is high) optDesign –postRoute –hold | -setup |

#PostRoute Via Optimization Replace single cut vias with multi-cut or fat vias to increase yield generateVias routeDesign –viaOpt

#EcoRouting #Fixing Max trans ecoAddRepeater –term U566/A –cell BUFFX4 report_constraint -drv_violation max_transition

ecoRoute setAttribute –net -skip_routing true setAttribute –net <eco_name> -skip_routing false

#Post Route RC Extraction setExtractRCMode –engine postRoute

#RC Extraction #Chip Finishing (Add filler cells) addFiller –cell –prefix –doDRC setMetalFill addMetalFill MetalFill

#To improve timing for critical nets for timing closure setMetalFill trimMetalFillNearNet

#Dump out GDS streamOut -mapFile –libName –merge –uniquifyCellNames –units –mode

#Check Timing timeDesign –signoff –outDir timeDesigb –signoff –hold –outDir

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