Ies Training 85166

Incisive Enterprise Simulation Training Yu Peng [email protected] 021-61222335

June 21, 2011

Course Objective Objective:  To simulate your Verilog design using an Incisive simulator

Module 1: Fundamentals:  Briefly describe Incisive simulation  Set up your environment for Incisive simulation  Compile, elaborate, and simulate your design and testbench  Debug your design with the textual

Module 2: Advanced Topics:  Debug your design with the graphical interfaces  Utilize additional simulation-related utilities  Annotate SDF timing data to the HDL portions of your design June 21, 2011

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Course Prerequisites What you need to already have:  A basic understanding of the design verification purpose and methods  A basic fluency in Verilog

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Agenda Day 1

Day 2

 Incisive simulation overview

 Debugging with the graphical interface

 Setting up the simulation environment

 Introduction to simulator utilities

 Compiling your design

 Optional topics:  Annotating SDF timing

 Elaborating your design  Simulating your design  Debugging with the textual interface

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Getting Additional Help Following slides suggest some sources for additional help with:  The Verilog language  The SystemVerilog language  The Cadence simulator

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Getting Help with the Verilog Language  Standards  IEEE Std. 1364-2005 http://www.ieee.org

 Advocacy group  Accellera http://www.accellera.org  EDA.org http://www.eda.org  News group

 http://groups.google.com/group/comp.lang.verilog  http://www.faqs.org/faqs/verilog-faq  Verilog Publications  Donald E. Thomas and Philip Moorby. “The Verilog Hardware Description

Language”. Springer (http://www.springer.com), 2009.  Cadence Documentation  Verilog®-XL Reference (http://sourcelink.cadence.com)

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Getting Help with the SystemVerilog Language  Standards  IEEE Std. 1800-2007 http://www.ieee.org

 Advocacy group  Accellera http://www.accellera.org  EDA.org http://www.eda.org  News group

 http://groups.google.com/group/comp.lang.verilog  http://groups.google.com/group/SystemVerilog  SystemVerilog Publications  Bergeron, J., Cerny, E. (et al.), “Verification Methodology Manual for

SystemVerilog”. Springer (http://www.springer.com), 2005.  Cadence Documentation  SystemVerilog Reference (http://sourcelink.cadence.com)

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Getting Help with the Simulator  Enter the -help command-line option when you invoke the tool  This displays brief help about available command-line options.

 Enter the interactive help command  This displays brief help about available interactive commands.  The graphical interface has context-sensitive balloon help and a Help menu  With the Help menu, you can access Guides, Product Notes, Known

Problems and Solutions, and Tutorials for the Cadence simulators and simulation analysis environment.  You can alternatively start the Cadence Help online documentation system

standalone by entering cdnshelp in a terminal window.  If you have a Cadence software service agreement you can also:

 Browse the searchable knowledge database http://.cadence.com  the Customer Response Center  By email: [email protected]  By phone: 800-820-2367 June 21, 2011

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Product Documentation Your installation of the product automatically installs product documentation. Use Cadence Help to access documents by product, manual or topic:  On the UNIX command line, enter: cdnshelp & – OR –

 From the GUI, select the Help menu in windows and Help button on forms

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Customer SourceLink Online Customer .cadence.com  Search the solution database and the

entire site.  Access all documentation.  Find answers 24x7.

If you don’t find a solution on the SourceLink site...

Submit a service request online.

If you have a Cadence software service agreement, you can get help from SourceLink online customer . The web site gives you access to application notes, frequently asked questions (FAQ), installation information, known problems and solutions (KPNS), product manuals, product notes, software rollup information, and solutions information.

Customer

Online Form From the SourceLink web site, fill out the Service Request Creation form.

Service Request

If your problem requires more than customer , then a product change request (PCR) is initiated.

PCR June 21, 2011

Incisive Enterprise Simulation training

R&D 10

Introduction to Incisive Simulation Chapter 1

June 21, 2011

Chapter Objective Objective:  To be able to describe Incisive simulation to your manager

Module topics:  Introduction to Incisive simulation  The Incisive verification platform  Interleaved Native Compiled-code Architecture (INCA)  Simulator of SystemC, VHDL, Verilog, and SystemVerilog

 The simulator library of derived design data  The simulator tool flow

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The Incisive Enterprise Simulator – XL

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Incisive Functional Verification Flows

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Native Compiled Code The simulator compiles HDL source code directly into executable code. Why?

Compared to an intermediate translation to C, this results in:  Reduced compilation time  Reduced execution time  Reduced memory requirements

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Interleaved Native Compiled Code Extensions to Native Compiled Code address the performance challenges of a single-simulation strategy:  Multiple representations — behavioral / RTL / gate / UDP

 Multiple languages — SystemC / VHDL / Verilog / SystemVerilog  Multiple paradigms — Cycle / Event  Mixed signal — Analog / Digital

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How Native Compiled Code is Interleaved Verilog

VHDL

Language X

Compile

Compile

Compile

VST

AST

???

Elaborate customized time update code

code object

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Verilog

k

VHDL

k

Language-X

k

Verilog

k

VHDL

k

Language-X

k

k: distributed event scheduling methods

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Verilog Language The simulator s these Verilog standards:  IEEE std. 1364-1995 Verilog Language Reference Manual  With some features subject to interpretation

 IEEE std. 1364-2001 Verilog Language Reference Manual  With some features subject to restrictions

 IEEE std. 1800-2005 Standard for SystemVerilog  With some features subject to restrictions

Plus proprietary system task/function extensions for design verification.

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Cadence System Task/Function Extensions Load or unload a serial scan chain

$broadside

Deposit a value to a Verilog net or

$deposit

Load ASCII stimulus vectors

$loadStimFileX, $loadStrobeFileX, $strobeStimX

Mirror the value of a VHDL signal or Verilog net

$nc_mirror

Deposit a value to a VHDL signal or Verilog net

$nc_deposit

Force a value on a VHDL signal or Verilog net

$nc_force

Release a forced VHDL signal or Verilog net

$nc_release

Transaction recording

$sdi_set_recording, $sdi_create_fiber, $sdi_transaction, (etc.)

Transition recording (to SHM)

$shm_open, $shm_probe, $shm_close

Transition recording (to VCD)

$recordfile, $recordvars, $signalscan, (etc.)

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Library-Based Design Data Management Design Hierarchy mychip cell1

cell2

File

Cell

View

mychip.p

mychip

sc_module worklib.mychip:sc_module

cell1.v

cell1

vlog

worklib.cell1:vlog

vhdl

WORKLIB.CELL1:VHDL

gate

worklib.cell2:gate

prim

WORKLIB.CELL2:PRIM

cell1.vhd cell2.v

Directory Hierarchy ./INCA_libs/ |_ cds.lib |_ hdl.var |_ worklib/ |_ *.pak ./my_source/ |_ mychip.p |_ cell1.v |_ cell1.vhd |_ cell2.v |_ cell2.vhd June 21, 2011

cell2

cell2.vhd

Reference

Cadence libraries HDL variables

virtual filesystem mychip cell1 cell2 | _|_ _|_ | | | | | Views/Architectures: sc_module vhdl vlog prim gate Modules/Entities:

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Running the Simulator Running the simulator is separated into three major steps: 1. Compilation with ncsc, ncvhdl, or ncvlog  Checks syntax and semantics

 Creates design data objects (SCD, AST, VST)  Creates SystemC and VHDL code objects (.o, COD)

2. Elaboration (expansion and linking) with ncelab  Constructs design hierarchy and connects signals

 Creates signature object (SIG) and Verilog code object (COD)  Creates initial simulation snapshot object (SSS)

3. Simulation with ncsim  Executes simulation code

Note: Separation of steps allows iteration of only the required steps!

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The Simulator Tool Flow SystemC

VHDL optimizer

ncsc

Verilog optimizer

ncvhdl g++

SCD

optimizer

ncvlog ncvhdl_cg

AST .so

ncvhdl_cg ncvlog_cg VST

COD COD ncelab

SIG

Path Legend primary transparent optional

SSS ncsim

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Tool Invocation Options You can choose from two ways to run the simulation:  Single-step invocation with irun  Simplifies multi-language simulation

 Accepts e, SystemC, VHDL and Verilog sources

 Multi-step invocation of compiler(s), elaborator and simulator  Complicates simulations that include SystemC or (especially) e

This training focuses on the multi-step mode only to promote your understanding. You may elect to use the single-step mode for most of your work.

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Summary You should now be able to describe Incisive simulation to your manager.

This chapter introduced Incisive simulation:  The Incisive verification platform  Interleaved Native Compiled-code Architecture (INCA)  Simulator of SystemC, VHDL, Verilog, and SystemVerilog  The simulator library of derived design data  The simulator tool flow

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Setting Up the Simulation Chapter 2

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Chapter Objective Objective:  To set up your simulation environment

Module topics :  Setting up the simulation environment  Create library directories  Create cds.lib and hdl.var files

 Optionally create a setup.loc file  Use the nchelp, ncls, and ncrm utilities

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Creating a cds.lib File The optional Cadence Libraries (cds.lib) file:  Is an ASCII file (easily edited)  Tells the simulator which libraries may be used  Tells the simulator where the libraries are located  Maps logical library names to physical directory locations INCLUDE $CDS_INST_DIR/tools/inca/files/cds.lib SOFTINCLUDE ${HOME}/cds.lib DEFINE aludesign ./design DEFINE ic_lib /usr1/libraries/lsi_library ASSIGN ic_lib TMP ./tmp_lib

This example cds.lib file includes a cds.lib file from the home directory and defines two additional libraries. It temporarily attaches a local directory to the ic_lib library, into which the simulator places derived ic_lib data.

DEFINE library path

Define library as the directory specified in path

UNDEFINE library

Undefine library (useful if defined in an included file)

INCLUDE file

Include file contents (file must be available)

SOFTINCLUDE file

Include file contents (if file is available)

ASSIGN library attribute value

Assign attribute and its value to library

UNASSIGN library attribute

Unassign attribute from library

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Creating an hdl.var File The optional HDL Variables (hdl.var) file:  Is an ASCII file (easily edited)  Contains environment variables  Default configuration variables, such as WORK  File name to library name mapping, such as LIB_MAP  Default command line options, such as NCVLOGOPTS  File name variables, such as NCSIMRC

INCLUDE $CDS_INST_DIR/tools/inca/files/hdl.var SOFTINCLUDE ${HOME}/hdl.var DEFINE WORK my_lib DEFINE VERILOG_SUFFIX ( .v, .vr, .vb, .vg )

This example hdl.var file includes the hdl.var file in the home directory, defines the work library to be my_lib, and defines several valid Verilog source file suffixes.

DEFINE variable value

Defines a variable and assigns a value to it

UNDEFINE variable

Undefine variable (useful if defined in an included file)

INCLUDE file

Include file contents (file must be available)

SOFTINCLUDE file

Include file contents (if file is available)

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HDL variables 28

Example hdl.var File DEFINE NCSCOPTS -errormax 10 -messages -compiler g++ DEFINE NCVHDLOPTS -errormax 10 -messages -v93 DEFINE NCVLOGOPTS -errormax 10 -messages -v1995 DEFINE NCELABOPTS -errormax 10 –messages DEFINE NCSIMOPTS -errormax 10 -messages –licqueue DEFINE NCSIMRC ./my_ncsimrc #DEFINE VIEW behav #DEFINE WORK worklib #specify valid source file extensions DEFINE VHDL_SUFFIX ( .vhd, .vhdl, .vh ) DEFINE VERILOG_SUFFIX ( .v, .vr, .vb, .vg )

#specify the source root directory DEFINE SRC_ROOT $MY_PROJECT/src #for ncvhdl & ncvlog - libraries into which to compile sources #for ncelab - library search order for Veristances DEFINE LIB_MAP (myfile.v => mylib, ./cell_lib => techlib, + => worklib)

#for ncvlog - views into which to compile Verilog sources #for ncelab - view search order for Veristances DEFINE VIEW_MAP (.vb => behav, .vr => rtl, .vg => gate, + => module)

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Creating a Library Map File The IEEE Verilog Std. 1364-2001 section 13 defines the library map file:  An ASCII file (easily edited)  Maps each Verilog source path to a library name  Maps each cell instance to a library name include ${HOME}/libmap.txt; library mylib myfile.v; library techlib cell_lib/; library worklib .../; config top_rtl; design worklib.top; default liblist worklib; instance u1 use mylib.u:config; cell ADD use techlib.ADD; endconfig

This example library map file includes a library map file from the home directory, maps three sets of Verilog source to libraries, and defines a configuration called top_rtl that binds the u1 instance to the mylib.u configuration and instances of the ADD cell to the techlib library.

include pathname ;

Include another library map file

library libname pathname [ { , pathname } ]

Declare a library

config configname; ... endconfig

State a configuration

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syntax 30

Creating a setup.loc File The optional setup locations (setup.loc) file:  Is an ASCII file (easily edited)  Specifies an alternative search order for the cds.lib and hdl.var files

The default search order for the cds.lib and hdl.var and setup.loc files is: 1. Current directory 2. $CDS_WORKAREA 3. $CDS_SEARCHDIR 4. $HOME 5. $CDS_PROJECT 6. $CDS_SITE 7. /share

The simulator must find a valid cds.lib file and a valid hdl.var file in this search. The simulator uses only the first cds.lib and hdl.var files found during the search, but you can use the INCLUDE keyword to explicitly include additional files. June 21, 2011

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Using the nchelp Utility Use nchelp to:

 Display libraries defined in a specific (or all loaded) cds.lib file(s)

Display variables defined in a specific (or all loaded) hdl.var file(s) nchelp [-options] {-cdslib | -hdlvar} [file_name] nchelp -cdslib ~/cds.lib nchelp -hdlvar

 Obtain a description of tool message codes nchelp [-options] {-all | tool_name} message_code nchelp ncvlog BADCLP nchelp ncelab CUVWSP

 You can alternatively just read the help message files in:

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Example Using the nchelp Utility

%ncvlog top.v -cdslib nosuch.cds -nocopyright ncvlog: *F,BADCLP: the -CDSLIB argument’s path nosuch.cds does not exist or is not readable. attempt to specify a cds.lib nchelp ncvlog BADCLP file that is not found ncvlog/BADCLP = The path specified for the -CDSLIB argument is invalid. Check that the specified path exists and is readable. %ncelab top -nocopyright attempt to elaborate a design drv u1 (out1); containing a dangling output port | ncelab: *W,CUVWSP (./top.v,2|5): 1 output port was not connected: ncelab: (./drv.v,1): out2 nchelp ncelab CUVWSP ncelab/CUVWSP = The indicated module instance does not specify a connection for each output port in the module port list. The specified output ports are left unconnected.

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Using the ncls Utility Use ncls to list the derived objects stored in the library system. ncls [-options] [lib.][cell][:view] ncls project_lib.top:module or ncls top -library project_lib -view module Just enter the arguments to list all objects of one or all views of a specified cell in one or all libraries. Omitting the library and view lists all objects of the cell.  Object selection options:  -code (COD), -snapshot (SSS), -verilog (VST), -overlay (SIG), -systemc (SCD), -vhdl

(AST)

 Unit type selection options:  -architecture, -body, -configuration, -connect, -entity, -interface, -module, -package, -

program, -primitive

 Information selection options:  -command, -dependents, -lockinfo, -messages, -no_std_ieee, -release, -source [-

absolute_path], -time

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Example Using the ncls Utility

%ncls -all –nocopyright module worklib.drv:module (VST) module worklib.drv:module (SIG) <0x5a85e48e> module worklib.dut:module (VST) module worklib.dut:module (SIG) <0x34683e01> module worklib.top:module (VST) module worklib.top:module (SIG) <0x01f0b280> module worklib.tst:module (VST) module worklib.tst:module (SIG) <0x638c9e1c> module worklib.tst:module (COD) <0x638c9e1c> snapshot worklib.top:module (SSS)

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Using the ncrm Utility Use ncrm to remove the derived objects stored in the library system. ncrm [-options] [lib.]cell[:view] ncrm project_lib.top:module

Just enter the arguments to remove one or all views of a specified cell from one or all libraries. Omitting the library and view removes all versions of the cell.

Interesting options include: -library <arg>

– Remove all elements of the specified library

-release <arg>

– Remove code (COD) objects of specified hotfix

-snapshot

– Remove only the snapshot (SSS) object

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Summary You should now be able to set up your simulation environment

This chapter discussed setting up the simulation environment:  Creating library directories  Creating the optional cds.lib and hdl.var files  Creating the optional setup.loc file  Using the nchelp, ncls, and ncrm utilities  You may need these for the following lab

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About Lab 1 For this introductory lab you can choose among two options:  Short option — Compile, elaborate, and simulate a 2-to-1 mux design

Choose this option if your time is constrained. In this lab you run a small Incisive simulation to become familiar with the library structure and tool invocation. This lab uses the textual interface to the simulator.  Longer option — Do the simulator tutorial

Choose this option if your time is less constrained. In this lab you read and follow the tutorial to compile, elaborate, simulate and debug a drink machine design. This lab uses the graphical interface to the simulator.

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Compiling Verilog Components Chapter 3

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Chapter Objective Objective:  To compile Verilog components

Module topics:  Compiling your design  Specify the source HDL location  Specify the destination library

 Maximize simulator performance

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Introducing the Verilog Compiler Compile your Verilog design units with the ncvlog compiler:

Verilog

 Checks syntax and semantics

optimizer

 Generates design data (VST)

ncvlog

 Produces ncvlog.log log file

ncvhdl_cg ncvlog_cg VST

COD ncelab

SSS

SIG

Path Legend primary transparent optional

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Conditional Compilation The Verilog parser recognizes two pre-defined macros:  CDS_TOOL_DEFINE  To conditionally compile Verilog code to be run by any Cadence tool

 INCA  To conditionally compile Verilog code to be run by the simulator only

`ifdef CDS_TOOL_DEFINE Cadence-specific Verilog code... `ifdef INCA Incisive simulator-specific Verilog code... `endif `endif

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Invoking the Verilog Compiler Use ncvlog to compile your Verilog sources.

 You can provide file name arguments ncvlog [-options] filename(s) ncvlog -messages 2bit_adder_test.v

 You can provide a compilation command file instead of source files ncvlog [-options] -cmdfile compilation_command_file ncvlog -messages -cmdfile 2bit_adder_test.cmd

 You can provide an individual design unit to recompile ncvlog [-options] -unit [lib.]cell[:view] ncvlog -messages -unit worklib.my_cell:my_view

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Specifying Compiler Source You can specify the compiler source with compiler options  By default Compile all design units in files listed on the command line

ncvlog alu_test.v alu.v

 -specificunit [lib.]cell[:view] Specify a single design unit to compile and optionally a library and view in which to store compiled units ncvlog alu.v -specificunit design_lib.arith:rtl

 -cmdfile filename Provide a compilation command file ncvlog -cmdfile 2bit_adder_test.cmd

 -unit [lib.]cell[:view] Specify a design unit to recompile (the original source must still be accessible) ncvlog -unit design_lib.arith

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Using a Compilation Command File A compilation command file specifies:  The top-level design configuration, source file or unit Define DESIGN_TOP top_rtl:configuration

You can override this with the -design_top option

 A search path for locating the source files (automatically includes .) Define SEARCH_PATH (./src_pads ./src_core ./src_test)

 Optionally, a file of unit name to source file name mapping rules Define RULES_FILE ./name_mapping_rules Otherwise uses the default naming rules

 Optionally, a value for the REDUMP_ON_UPDATE variable Whether to also recompile unmodified source files (normally on) Define REDUMP_ON_UPDATE off

 Optionally, a string of compiler options DEFINE VLOG_ARGS (-messages –v1995)

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Specifying Destination Library and View This section individually discusses:  Defaulting the destination library and view  Specifying the library and view with variables  Specifying the library and view with compiler options  Specifying the library and view with compiler directives

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Defaulting the Destination Library and View If you do not specify the library, the compiler uses:  library worklib

(If cds.lib file absent)

 no default library

(If cds.lib file present)

If you do not specify the view, the compiler uses:  view module (If it is a module)  view udp

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(If it is a UDP)

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Using the LIB_MAP and VIEW_MAP Variables You can specify the destination library and view with the LIB_MAP and VIEW_MAP variables. You can define these variables in the hdl.var file:  LIB_MAP Map files and directories to library names Define LIB_MAP (mine.v => mylib, ./src => srclib, + => worklib)

 VIEW_MAP Map file extensions to view names Define VIEW_MAP (.vb => behav, .vr => rtl, .vg => gate, + => module)

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Using a Library Map File You can specify the destination library with an IEEE-standard library map file. Provide the library map file to the compiler with the libmap option:  -libmap library_map_file Specify the library map file. The library map file associates each source path with a library. You must define the libraries in the cds.lib file. This option overrides the LIB_MAP variable. ncvlog counter.v -libmap libmap.txt

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library map file

library mlib top.v; library lib1 sub1.v; library lib2 sub2.v; config top; design top; default liblist mlib lib1 lib2; instance top.sub1 use lib1.sub; instance top.sub2 use lib2.sub; endconfig

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Using the WORK and VIEW Variables You can specify the destination library and view with the WORK and VIEW variables. You can define these variables in the hdl.var file:  WORK Specify the library in which to store compiled objects. This variable overrides the LIB_MAP variable and the -libmap option. Define WORK worklib

 VIEW Specify the view in which to store compiled objects. This variable overrides the VIEW_MAP variable. Define VIEW gate

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Using the work and view Options You can specify the destination library and view with compiler options:  -work library_name Specify the library in which to store compiled objects. This option overrides the WORK and LIB_MAP variables and the libmap option. ncvlog counter.v -work design_lib

 -view view_name Specify the view in which to store compiled objects. This option overrides the VIEW and VIEW_MAP variables.

ncvlog top.v -view behav

 -specificunit [lib.]cell[:view] Specify a single design unit to compile and optionally a library and view in which to store the compiled objects. This option overrides the work and view options.

ncvlog alu.v -specificunit design_lib.arith:rtl

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Using the `worklib and `view Directives You can specify the destination library and view with compiler directives:  `worklib (cancel with `noworklib)  Specifies the library in which to store compiled objects

 Overrides all other methods of specifying the library

 `view (cancel with `noview)  Specifies view in which to store compiled objects  Overrides all other methods of specifying the view

`worklib design_lib `view rtl module alu(...); // definition... endmodule `noworklib `noview

The IEEE Std. 1364 does not reference the `worklib and `view compiler directives. These are vendor directives specific to the Cadence simulator. June 21, 2011

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Summarizing the Methods to Specify Library and View From highest to lowest precedence, here are the methods again: To specify the library

To specify the view

Where to specify

`worklib library

`view view_name

Compiler directive

-specificunit [lib.]cell[:view]

-specificunit [lib.]cell[:view]

Compiler option

-work library

-view view_name

Compiler option

Define WORK library

Define VIEW view_name

HDL variable

-libmap library_map_file Library library source(s)

not applicable

Compiler option Library map file

Define LIB_MAP lib_map

Define VIEW_MAP view_map

HDL variable

No default

Defaults to “module” or “udp”

Default

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Optimizing Performance  -update

Suppress compilation of already up-to-date units. This option can affect compiler performance positively or negatively. ncvlog fifo.v -update

 -linedebug

Enable for all line debug operations.

This option negatively impacts subsequent simulation performance! ncvlog fifo.v -linedebug

 -noline

Suppress display of source code with error messages. ncvlog fifo.v –noline

 The compiler by default runs with performance optimizations enabled! June 21, 2011

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Miscellaneous Compiler Options  -define variable [=value]

Define a text macro and optionally assign to it a value ncvlog -define debug_mode=1 top.v

 -libcell

Tag compiled modules as library cells ncvlog -libcell cell_lib.v

 -sv

Enable SystemVerilog constructs ncvlog -sv top.v

 -v1995

Favor Verilog 1995 constructs ncvlog -v1995 top.v June 21, 2011

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Verilog Compiler HDL Variables LIB_MAP

Map of source files and directories to library names Define LIB_MAP (mine.v => mylib, ./src => srclib, + => worklib)

VIEW_MAP

Map of source file extensions to view names Define VIEW_MAP (.vb => behav, .vr => rtl, .vg => gate, + => module)

NCUSE5X

Create the full Cadence 5.X standard library for interoperability Define NCUSE5X

NCVLOGOPTS

ncvlog compiler invocation options Define NCVLOGOPTS -errormax 10 -messages

SRC_ROOT

Source root directories Define SRC_ROOT (~/mylib/src, $PROJECT/source)

VERILOG_SUFFIX

Verilog source file extensions, initially (.v) DEFINE VERILOG_SUFFIX ( .v, .vr, .vb, .vg )

VIEW

View of compiled unit Define VIEW gate

WORK

Library of compiled unit Define WORK worklib

June 21, 2011

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Summary You should now be able to compile Verilog components.

This chapter discussed:  Specifying the source HDL location  Specifying the destination library  Maximizing subsequent simulator performance

June 21, 2011

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About Lab 2 This lab is in two parts. Be sure to complete both parts, as you will use the components in later labs. These labs focus on compilation aspects and explore compiler options.  In the first lab, you compile, elaborate, and simulate a design and its

testbench.  In the second lab, you compile, elaborate, and simulate a counter design and its

testbench.

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Elaborating Your Design Chapter 4

June 21, 2011

Chapter Objective Objective:  To elaborate the design

Module topics:  Elaborating your design  Specify the top-level design units to elaborate  Specify the design configuration

 Specify the destination snapshot name  Maximize subsequent simulator performance

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Introducing the Elaborator Elaborate (expand and link) your design with the ncelab elaborator:  Constructs design hierarchy and connects signals  Creates signature object (SIG) and code object (COD)  Creates initial simulation snapshot object (SSS)  Produces ncelab.log log file

SCD

AST

VST

.so

ncelab

SIG

Path Legend primary transparent optional

SSS ncsim

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Invoking the Elaborator Use ncelab to elaborate your design. The argument can be either a:  Compiled VHDL configuration or at least one compiled top level design unit At most one SystemC top and at most one VHDL top

ncelab [options] [lib.]cell[:view] ... ncelab -messages top

 Verilog configuration in a library map file ncelab [options] -libmap library_map_file configuration_name

ncelab -messages -libmap libmap top_config

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Specifying Top-Level Design Units to Elaborate This section individually discusses:  Defaulting the top-level specification  Specifying top-level design units with the WORK variable  Specifying top-level design units with the -work option  Explicitly specifying the top-level design units

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Defaulting the Top-Level Specification You can default the top-level unit specification:  ncelab [options] top_level_unit(s) You can omit the library specification if each top-level cell exists in only one library.

You can omit the VHDL architecture specification to use that most recently analyzed. You can omit the Verilog view specification if only one view exists in that library. ncsc: ncelab top -loadsc libncsc vhdl: ncelab top vlog: ncelab top

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Using the WORK Variable You can restrict the search for top-level units with the WORK variable:  Define WORK work_library Specify a library for the elaborator to search for the specified top-level cells.

All specified top-level cells must exist in that library. cds.lib

INCLUDE $CDS_INST_DIR/tools/inca/files/cds.lib Define WORK worklib ncsc: ncelab top -loadsc libncsc vhdl: ncelab top vlog: ncelab top

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Using the work Option You can restrict the search for top-level units with the -work option.  -work work_library Specify a library for the elaborator to search for the specified top-level cells.

All specified top-level cells must exist in that library. This option overrides and works the same as the WORK variable: ncsc: ncelab top -work worklib -loadsc libncsc vhdl: ncelab top -work worklib vlog: ncelab top -work worklib

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Explicitly Specifying Top-Level Design Units You can explicitly specify the top-level design units:  ncelab [options] [lib.]cell[:view] ... Explicitly specify on the command line the library and/or view for the elaborator to search for a top-level design unit. ncsc: ncelab worklib.top:sc_module -loadsc libncsc vhdl: ncelab worklib.top:vhdl vlog: ncelab worklib.top:module

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Summarizing the Methods to Specify Top-Level Units From highest to lowest precedence, here are the methods again: To specify the library

To specify the view

Where to specify

[lib.]cell[:view]

[lib.]cell[:view]

Elaborator argument

-work library

VHDL: MRA Verilog: Library has one view

Elaborator option

Define WORK library

VHDL: MRA Verilog: Library has one view

HDL variable

Search all defined libraries VHDL: MRA Verilog: Libraries have one view

Default

If the elaborator defaults to searching for top-level units through all defined libraries, each toplevel cell must exist in exactly one library and only one Verilog view may exist in that library.

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Specifying Verilog Subunits to Bind This section individually discusses:  Defaulting the subunit binding  Specifying subunits with HDL variables  Specifying subunits with elaborator options  Specifying subunits with compiler directives  Specifying subunits with a library map file

The IEEE Std. 1364-2001 describes Verilog configurations. Other binding rules this subsection describes are specific to the Cadence simulator.

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Defaulting the Binding You can default the subunit binding:  ncelab [options] top_level_unit(s) Do not specify the library or view in which to find subunits

ncelab top

The elaborator searches for the subunit in this order: 1. It searches the cds.lib libraries and “module” and “udp” views in order, starting

with the library and view in which it found the definition of the subunit parent, and wrapping around to the beginning of the list if necessary. 2. It searches for any view in the library in which it found the definition of the

subunit parent, and if only one view exists, uses it. 3. It searches for any view in any library defined in the cds.lib file, and if only one

view exists, uses it.

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Using the LIB_MAP and VIEW_MAP Variables You can specify the subunit search order with the LIB_MAP and VIEW_MAP variables:  LIB_MAP Specify libraries and the order to search them Define LIB_MAP ( ./src => projlib, lib.v => techlib, + => worklib )

 VIEW_MAP Specify views and the order to search them Define VIEW_MAP ( .vr => rtl, .vg => gate, + => module )

The elaborator searches the LIB_MAP libraries and VIEW_MAP views in order, starting with the library and view in which it found the definition of the subunit parent and wrapping around to the beginning of the list if necessary.

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Using the libname and viewname Options You can specify the subunit search order with elaborator options:  -libname library_name Specify libraries and the order to search them. Overrides LIB_MAP. ncelab top -libname techlib -libname worklib

 -viewname view_name Specify views and the order to search them. Overrides VIEW_MAP. ncelab top -viewname gate -viewname module

You can specify a subunit binding with an elaborator option:  -binding [lib.]cell[:view] Explicitly specify a library and/or view with which to resolve all references to a cell. This option overrides -libname and -viewname options and the LIB_MAP and VIEW_MAP variables. ncelab top -binding foo:rtl

The version 9.2 documentation does not describe the -viewname option. These training materials describe this undocumented option for historical purposes. Although the elaborator still accepts this option, your use of it unnecessarily complicates the subunit resolution process.

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Using the `uselib Directive You can specify a subunit binding with a compiler directive:  `uselib lib = (cancel with `nouselib or empty `uselib)  Specifies the library in which to resolve references  Overrides all other options and variables

 `uselib view = (cancel with `nouselib or empty `uselib)  Specifies the view in which to resolve references  Overrides all other options and variables

module u ();

`uselib lib = design_lib `uselib view = rtl alu alu1 (dataout,datain,op); `nouselib . . .

endmodule The IEEE Std. 1364 does not reference the `uselib compiler directive. This directive is specific to the Cadence simulator. June 21, 2011

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Using a Library Map File You can specify the design configuration with a library map file. Provide the library map file to the elaborator with the -libmap option.  -libmap library_map_file Specify the library map file. The library map file specifies configurations for each design unit to elaborate. You must define the libraries in the cds.lib file. The library map file overrides all other methods to specify the library in which to find subunit definitions. ncelab top -libmap libmap.txt

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library map file

library mlib top.v; library lib1 sub1.v; library lib2 sub2.v; config top; design top; default liblist mlib lib1 lib2; instance top.sub1 use lib1.sub; instance top.sub2 use lib2.sub; endconfig

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Summarizing the Methods to Specify the Subunits From highest to lowest precedence, here are the methods again: To specify library order

To specify view order

Where to specify

config ... endconfig

not applicable

Library map file

`uselib lib = library

`uselib view = view_name

Compiler directive

-binding [lib.]cell[:view]

-binding [lib.]cell[:view]

Elaborator option

-libname library

-viewname view_name

Elaborator option

Define LIB_MAP lib_map

Define VIEW_MAP view_map

HDL variable

Search in cds.lib order

Search for “module”, then “udp” Default

Search parent library

Search for any view

Default

Search all cds.lib libraries Search for any view

Default

The version 9.2 documentation does not describe the -viewname option. These training materials describe this undocumented option for historical purposes. Although the elaborator still accepts this option, your use of it unnecessarily complicates the subunit resolution process.

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Specifying the Snapshot Name You can specify the snapshot name with an elaborator option:  By default Store the simulation snapshot in the lib.cell:view of the VHDL top-level design unit, or if none, then in the lib.cell:view of the first of the top-level design units listed on the command line. ncelab top

 -snapshot [lib.]cell[:view] Explicitly specify a library, cell, or view in which to store a snapshot.

ncelab top -access RWC -snapshot debug

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Miscellaneous Elaborator Options This section individually discusses some elaborator options associated with:  Providing debug access to HDL objects  Optimizing simulator performance  Annotating SDF timing data  Controlling simulation timing  Using enhanced Verilog timing features  Dynamically ing Verilog PLI/VPI applications

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Providing Debug Access to HDL Objects Option

Description

-access [+] [-] access

Set the default global design object access control: R – read, W – write/read, C – connectivity/read

-ncinitialize

[Verilog] Retain RW access to variables for initialization

-show_forces

[Verilog] Enable simulator to show Verilog code forces. Requires access.

-afile filename

Provide a file of design object access controls that override the default global design object access controls

-genafile filename

Generate an access control file while running simulation

ncelab top -genafile my_afile ncsim top ncelab top -afile my_afile Example access file

BASENAME top.DUT // set the base to the top.DUT level of hierarchy PATH *.*.* +R //set read access to three levels below top.DUT PATH ... REG +R //set read access to reg data types at top.DUT and below CELLLIB worklib.bigmem +RWC // add full access to cell worklib.bigmem

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Optimizing Simulator Performance The simulator runs in performance mode “out of the box”. Most switches that enable non-default features negatively impact performance. The following switches disable features and thus positively impact performance.  Turn off output  Common: -neverwarn, -nocopyright, -nolog, -no_sdfa_header, -nostdout, -

no_tchk_msg, -nowarn, -sdf_no_warnings  VHDL: -no_vpd_msg

 Verilog: -plinooptwarn, -plinowarn

 Turn off or relax timing features  Common: -notimingchecks, -sdf_precision  VHDL: -noipd, -no_tchk_xgen, -no_vpd_xgen, -vhdl_time_precision  Verilog: -delay_mode, -disable_enht, -noautosdf, -noneg_tchk, -nonotifier, nospecify

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Controlling Simulation Timing Option

Description

-{max, min, typ}delays

Select specified timing set

-no_tchk_msg

Disable timing check warning messages

-notimingchecks

Disable timing checks

-ntc_warn

Enable convergence warnings for negative timing checks

Table does not include annotation or language-specific options.

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Controlling Simulation Timing: Verilog Option

Description

-delay_mode mode

Delay mode {zero, unit, path, distributed}

-disable_enht

Disable enhanced timing features that reschedule module output transitions

-extend_tcheck_data_limit -extend_tcheck_reference_limit

Extend negative timing check limits to permit convergence

-nospecify

Disable specify timing (and SDF annotation)

-seq_udp_delay delay

Specify delay for all sequential UDPs and zero all other delays

-tfile filename

Provide a timing file to disable timing in specified Verilog portions of the design

ncelab top -tfile my_tfile

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Annotating SDF Timing Data Option

Description

-intermod_path

Enable multi-source interconnect delays

-no_sdfa_header

Suppress display of SDF header information

-sdf_cmd_file filename

Provide an SDF command file

-sdf_no_warnings

Suppress display of SDF annotator warnings

-sdf_precision precision

Specify maximum precision for SDF data

-sdf_verbose

Display detailed SDF annotator activity

Incomplete table – See the SDF Annotation chapter.

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Dynamically ing Verilog PLI/VPI Applications You Verilog PLI applications while invoking the elaborator because all PLI applications contain a call within the Verilog source code. You Verilog VPI -defined system tasks/functions while invoking the elaborator because they contain a call within the Verilog source code. You can optionally VPI callbacks while invoking the simulator because they do not contain a call within the Verilog source code. You all VHDL applications while invoking the simulator. Option

Description

-loadpli1 library:boot_function

Dynamically a PLI application

-loadvpi library:boot_function

Dynamically a VPI application

See the Applications Programming chapter.

ncelab top -loadpli1 vendor.so:boot_routine ncelab top -loadvpi vendor.so:boot_routine

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Miscellaneous Elaborator Options  -partialdesign, -nobinding cell

Permit creation of a not simulatable snapshot of a partial design, useful for examining an incomplete design hierarchy

ncelab top -partialdesign -nobinding sub simvision -snapshot top

 -gpg obj=>val, -generic obj=>val, -defparam obj=val

Initialize generics/parameters globally and/or specifically ncelab vhdltop \ -gpg "obj1=>2" \ -generic ":vhdlinst1:obj1=>3" \ -defparam :vst1.obj1=4

 -sparsearray size

Implement as a sparse array any one-dimensional array of reg vector, integer, or time having the specified number of elements or more ncelab top -sparsearray 1024 June 21, 2011

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Elaborator HDL Variables LIB_MAP

Ordered library search list for Verilog design subunit reference resolution Define LIB_MAP (mine.v => mylib, ./src => srclib, + => worklib)

VIEW_MAP

Ordered view search list for Verilog design subunit reference resolution Define VIEW_MAP (.vb => behav, .vr => rtl, .vg => gate, + => module)

NCELABOPTS

ncelab elaborator invocation options Define NCELABOPTS -errormax 10 -messages

WORK

Define a work library in which to find top-level design units Define WORK worklib

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Summary You should now be able to elaborate the design.

This chapter discussed:  Specifying the top-level design units to elaborate  Specifying the design configuration  Specifying the destination snapshot name  Maximizing subsequent simulator performance

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About Lab 3 This lab focuses on elaboration aspects and explores elaborator options. Complete all three parts, as you will use the components in later labs. In the first lab, you compile, elaborate, and simulate an ALU design and its testbench 8

8

accum

data

In the second lab, you compile, elaborate, and simulate a memory design and its testbench

w

aw a

alu write

aluout 8

June 21, 2011

mem s

3

w

addr read

opcode

In the third lab, you compile, elaborate, and simulate a scalable multiplexor design and its testbench

data

zero

dw

Incisive Enterprise Simulation training

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smx y w

87

Simulating Your Design Chapter 5

June 21, 2011

Chapter Objective Objective:  To simulate the design

Module topics:  Simulating your design  Specify the simulation snapshot  Specify the simulation run mode

 Automatically update your design  Maximize simulator performance

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Introducing the Simulator Simulate your design with the ncsim simulator:  Loads simulation snapshot (SSS) library object  Loads native-compiled code (COD) library objects  Optionally loads design data objects (AST, SCD, VST)  Optionally reads command and script files  Produces ncsim.log log file and ncsim.key key file

.so

SSS AST

Path Legend primary transparent optional

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SCD

VST

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Invoking the Simulator Use ncsim to simulate your design: ncsim [options] [lib.]cell[:view] ncsim -gui -run u_test

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“snapshot” (SSS object)

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Specifying the Simulation Snapshot  You can search for the snapshot through all the cds.lib libraries

You can omit the library and view specification only if the libraries contain exactly one representation of the snapshot to simulate. ncsim [options] cell ncsim u_test  With an HDL variable you can restrict the snapshot search to just one library

Specify a library for the simulator to search for the snapshot. It must contain exactly one representation of the snapshot. Define WORK work_library ncsim u_test

Set HDL variable WORK (perhaps in hdl.var)

 You can explicitly specify the snapshot library and/or view

Explicitly specify on the command line the library and/or view for the simulator to search for the snapshot. ncsim [options] [lib.]cell[:view] ncsim worklib.u_test:debug June 21, 2011

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Summarizing the Methods to Specify the Snapshot From highest to lowest precedence, here are the methods again: To specify the library

To specify the view

Where to specify

[lib.]cell[:view]

[lib.]cell[:view]

Command line

Define WORK library

Library must have one view

HDL variable

Search all defined libraries Libraries must have one view

Default

If the simulator defaults to searching for the snapshot through all defined libraries, only one library may contain the snapshot.

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Specifying the Simulation Run Mode To run the simulator interactively  -gui

To run the simulator non-interactively  Default mode

Invoke the simulator with the SimVision graphical interface

Simulate in non-interactive mode

ncsim [-run] u_test

ncsim -gui u_test

 -tcl

 -batch

Invoke the simulator with the Tcl command-line interface

ncsim -tcl u_test

Override a -tcl option (perhaps in NCSIMOPTS variable) ncsim -batch u_test

 -run Start simulation immediately without waiting for command input ncsim -gui -run u_test ncsim -tcl -run u_test

 -exit Explicitly exit simulation upon executing a Verilog $stop system task or upon simulation completion ncsim u_test \ -input my_script.tcl exit

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Summarizing the Methods to Specify the Run Mode Use these simulator options to specify the run mode: Noninteractive

Interactive (GUI)

Interactive (Tcl)

Load & Stop

—

-gui

-tcl

Load & Run

Default mode

-gui -run

-tcl -run

The following cause entry into interactive mode:  Invocation with the -gui or -tcl option  Control-c keyboard interrupt  Executing a Verilog $stop system task  The Tcl script does not run simulation to completion

The -batch option overrides the -tcl option. The -run option causes an interactive simulation to first run to suspension (Control-c interrupt or $stop executed) or completion (no more events to process or $finish executed) before returning to the ncsim> prompt. The -exit option causes a completed or suspended simulation to exit (unless suspended by the Control-c interrupt). June 21, 2011

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Miscellaneous Simulator Options This section individually discusses some simulator options associated with:  Initializing Verilog variables  Simulating with incremental update  Reading command scripts  Handling license queuing  Dynamically loading applications  Optimizing simulator performance

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Initializing Verilog Variables Option

Description

-ncinitialize value

Initialize persistent integral Verilog variables. value is one of { 0, 1, Z, X, rand:[int], rand_2state:[int] }

Only variables with read/write access are initialized. For random initialization you can provide a 32-bit integer seed (default is 0), e.g. ncvlog test.v ncelab test -ncinitialize

ncsim test -ncinitialize rand:42 -tcl ncsim> value %b my_int 32'b0zxzzx00zzzz0zz0z100zzzxzxzzx00z

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Simulating with Incremental Update Option

Description

-update

Update (compile and elaborate) out-of-date HDL design units

-nosource

Do not update (compile) source. Use -nosource with update to re-elaborate a design (with potentially out-of-date compiled units).

-uptodate_messages

Include in the status report those modules that are already up to date. Use -uptodate_messages only with -update.

-cmdfile filename

If you compiled VHDL using a compilation command file then you need to provide it when updating the design

June 21, 2011

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Reading Command Scripts Option

Description

-input file_name

Input Tcl commands from a file

-input @"tcl_command"

Input Tcl commands from a string

ncsim -input setup.tcl u_test ncsim u_test -input @"stop -line 22 u_test"

June 21, 2011

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Handling License Queuing Option

Description

-licqueue

Use license queue mechanism

-noliromote

Do not promote licenses

-uselicense string

Specify license promotion order

-nolicsuspend

Do not release licenses when simulation suspends

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Dynamically ing Verilog PLI/VPI Applications You Verilog PLI applications while invoking the elaborator because all PLI applications contain a call within the Verilog source code. You Verilog VPI -defined system tasks/functions while invoking the elaborator because they contain a call within the Verilog source code. You can optionally VPI callbacks while invoking the simulator because they do not contain a call within the Verilog source code. You all VHDL applications while invoking the simulator. Option

Description

-loadcfc library:boot_function

Dynamically a CFC application

-loadfmi library:boot_function

Dynamically a FMI application

-loadvhpi library:boot_function

Dynamically a VHPI application

-loadvpi library:boot_function

Dynamically a VPI application

See the Applications Programming chapter.

ncsim top -loadvhpi vendor.so:boot_routine ncsim top -loadvpi vendor.so:boot_routine June 21, 2011

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Optimizing Simulator Performance The simulator runs in performance mode “out of the box”. Most switches that enable non-default features negatively impact performance. The following switches disable features and thus positively impact performance. -epulse_no_msg

[Verilog] Suppress e-pulse error message

-neverwarn

Suppress all warning messages

-nocifcheck

[VHDL] Suppress VHDL design access function constraint check

-nocopyright

Suppress copyright banner

-nokey

Suppress keyfile

-nolog

Suppress logfile

-nontcglitch

[Verilog] Suppress negative timing check glitch messages

-nostdout

Suppress standard output

-nowarn <arg>

Suppress specific warning message

-plinooptwarn

[Verilog] Suppress PLI messages caused by no access

-plinowarn

[Verilog] Suppress all PLI warning and error messages

-redmem

Use reduced memory image size

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Profiling the Simulation The profiler identifies the modules and statements in your source description that use the most U time during simulation. Once you have this information you can investigate rewriting these constructs.  Use -profile to enable profiling (-sprofile to enable profiling and VHDL

statement counts)  Add -profthread if you have a threaded C application  Add -dut_prof file to separate DUT from testbench

# Comment dut:lib.cell:view dut:lib.cell:view other:lib.cell:view

 The profiler samples the simulation 100 times per U second, recording what

code line or simulator function is currently executing  The -profile or -sprofile option writes three tables to nrof.out  Detailed full profile ranking  Profile ranking by module

 Profile ranking by sample type

 The -sprofile option writes a per-statement execution count to

ncvhdl_sprofile.out June 21, 2011

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Example Profiler Output ncsim: 09.20-p007: (c) Copyright 1995-2009 Cadence Design Systems, Inc. SunOS acae240 5.10 Generic_118833-33 sun4u sparc Sun_Microsystems SUNW,Sun-Blade-2500, 2 Us, 1600 MHz, 4096 Meg RAM, 100 hits/sec, (mikep) ... Memory Usage - 37.8M program + 4.9M data + 1.0M profile = 43.7M total U Usage - 0.0s system + 1.0s = 1.1s total (100.0% u) -----------------------------------------------------------Stream Counts (96 hits total) -----------------------------------------------------------%hits #hits #inst name 45.8 44 [ ] Method SSS_KM_CL2TA (method) 15.6 15 [ 1] Always stmt (file: ./top.vlog, line: 29 in worklib.top [module]) 7.3 7 [ ] Method SSS_KM_FINDRFT (method) 6.2 6 [ 1] Always stmt (file: ./top.vlog, line: 9 in worklib.top [module]) 5.6 5 [ 1] Logic primitive 'nand' (zero delay) (method) ... -----------------------------------------------------------Most Active Modules (behavioral) -----------------------------------------------------------%hits #hits #inst name 33.3 32 [ 1] worklib.top:vlog (file: ./top.vlog line: 3) -----------------------------------------------------------Stream Type Summary Counts (96 hits total) -----------------------------------------------------------%hits #hits #inst name 56.2 54 [ ] Standard methods (mostly fanout propagation) 21.9 21 [ 2] Always statements 9.4 9 [ ] Logic primitives 8.3 8 [ 4] Non-blocking assignments 3.1 3 [ 1] Continuous assignments 1.0 1 [ ] Outside engine

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Simulator HDL Variables NCSIMOPTS

ncsim simulator invocation options Define NCSIMOPTS -errormax 10 -messages

NCSIMRC

Command file to automatically execute upon invocation Define NCSIMRC my_ncsimrc

WORK

Define a work library in which to find top-level design units Define WORK worklib

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Summary You should now be able to simulate the design.

This chapter discussed:  Specifying the simulation snapshot  Specifying the simulation run mode  Automatically updating your design  Maximizing simulator performance

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About Lab 4 This lab focuses on simulation aspects and explores simulation options. For this lab you compile, elaborate, and simulate a controller design and testbench. 0

1

2

3

4

5

6

7

clk sel

sel opcode rd ld_ir zero inc_pc ctl halt clk ld_pc data_e rstn ld_ac wr

rd

ALUOP

ld_ir inc_pc halt

SKZ JMP HALT

ld_pc

JMP

data_e ld_ac

STO ALUOP

rd

STO ALUOP is ADD | AND | XOR | LDA

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Debugging with the Command Line Interface Chapter 6

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Chapter Objective Objective:  To use the command line interface to interact with the simulator

Module topics:  Debugging with the textual interface  Enter the interactive simulation mode  Examine and traverse the design

 and much more!

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What is Tcl?  The Tool Command Language, a textual interface to software tools  Your command-line interface to the simulator

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What Can I Do with Tcl? You can execute Tcl commands interactively or from a script to:  Examine and traverse the design (find, scope, describe, drivers)  Read and write simulation objects (value, force, deposit)  Monitor signals (strobe)  Set breakpoints and run the simulation (stop, run)  Capture waveform data (database, probe)  Use the command history list (history)  Execute commands from a script (input, pause, source)  Save, reset, and restart the simulation (save, reset, restart)  Exit the simulator (finish, exit)

 and more...

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Entering the Interactive Mode Enter the interactive mode by interrupting the simulation:  Invoke ncsim with the -tcl command line option  Enter a Control-c asynchronous interrupt  Execute the Verilog $stop system task  Activate a breakpoint

When you interrupt the simulator, it enters interactive mode and prompts you: ncsim>

While the simulation is suspended, all signals retain their current state.

You can enter interactive commands at the prompt, and then resume simulation. Until you complete the current command, Tcl instead prompts with: >

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Command Overview: Standard Tcl Commands You can use any standard Tcl commands in your debug session: append

error

gets

linsert

puts

source *

array

eval

glob

list

pwd

split

break

exec

global

llength

read

string

case

exit *

history *

lrange

regexp

switch

catch

expr

if

lreplace

regsub

tell

cd

file

incr

lsearch

rename

trace

close

flush

info

lsort

return

unset

concat

for



open

scan

uplevel

continue

foreach

lappend

pid

seek

upvar

eof

format

lindex

proc

set

while

You can get help with the standard Tcl commands from SourceForge (http://tcl.sourceforge.net/) and the Tcl Developer Xchange (http://www.tcl.tk/). The Incisive Simulator Tcl Command Reference online document and the Tcl help command partially document the standard Tcl commands marked here with an asterisk (*).

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Command Overview: Tcl Command Extensions The simulator offers several additional Tcl commands: alias

database

fmibkpt

pause

run

strobe

analog

deposit

force

power

save

task

assertion

describe

heap

probe

scope

tcheck

attribute

drivers

help

process

simvision

time

call

dumpsaif

input

profile

sn

value

check

dumptcf

loopvar

release

stack

version

constraint

find

memory

reset

status

where

coverage

finish

omi

restart

stop

For brief help on debugging commands, enter help or help command from the interactive mode. For a detailed description, refer to the Incisive Simulator Tcl Command Reference online document.

Also see reference appendix

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Example Design Many commands on following pages refer to this simple design:  The clock, d-flipflop and multiplexor are built with primitives  The d7 reset input is not driven (connected to “rtsn” instead of “rstn”)  The d2 and d3 output “q” both drive the q[2] signal

rgs_test

 The q[3] signal is not driven

c1 dffr dffr dffr dffr dffr dffr dffr dffr

d7 d6 d5 d4 d3 d2 d1 d0

d7 d6 d5 d4 d3 d2 d1 d0

entity entity entity entity entity entity entity entity

: : : : : : : :

( ( ( ( ( ( ( (

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q[7], q[6], q[5], q[4], q[2], q[2], q[1], q[0],

, , , , , , , ,

n[7], n[6], n[5], n[4], n[3], n[2], n[1], n[0],

clk, clk, clk, clk, clk, clk, clk, clk,

work.dffr(vhdl) work.dffr(vhdl) work.dffr(vhdl) work.dffr(vhdl) work.dffr(vhdl) work.dffr(vhdl) work.dffr(vhdl) work.dffr(vhdl)

rtsn rstn rstn rstn rstn rstn rstn rstn

port port port port port port port port

) ) ) ) ) ) ) )

; ; ; ; ; ; ; ;

map map map map map map map map

( ( ( ( ( ( ( (

q(7), q(6), q(5), q(4), q(2), q(2), q(1), q(0),

open, open, open, open, open, open, open, open,

n(7), n(6), n(5), n(4), n(3), n(2), n(1), n(0),

Incisive Enterprise Simulation training

r1

m0

m4

d0

d4

m1

m5

d1

d5

m2

m6

d2

d6

m3

m7

d3

d7

clk, clk, clk, clk, clk, clk, clk, clk,

rtsn rstn rstn rstn rstn rstn rstn rstn

) ) ) ) ) ) ) )

; ; ; ; ; ; ; ; 115

Finding HDL Design Objects find — Find design objects find [options] regular_expression(s) ncsim> probe -shm [find -scope rgs_test.r1.d0 -ports *]

You can provide multiple object names, and you can wildcard the object names: ncsim> find carry ncsim> find carry out ncsim> find ca* ncsim> find *

Also see reference appendix

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Setting and Getting the Debug Scope  scope

— Display the current debug scope name

 scope -history — List recently visited scopes in order of visitation

 scope -set

— Set the debug scope

ncsim> scope rgs_test.r1  scope -show — Display information about the current debug scope

Instances at current debug scope, Current debug scope, Top-level units

ncsim> scope –show Directory of scopes at current scope level: module (rgs), instance (r1) module (clock), instance (c1) task (expect) Current scope is (rgs_test) Highest level modules: rgs_test  scope -tops June 21, 2011

— Display top-level design unit names Incisive Enterprise Simulation Training

Also see reference appendix 117

Getting the Simulation Location where — Display the current simulation location  If executing a process  Displays line number, file and scope of breakpoint, and current debug scope

 If updating a signal  Displays time of breakpoint, and current debug scope

ncsim> where Line 32, file "./rgs_test.v", scope (rgs_test) Scope is (rgs_test.r1)

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Listing HDL Design Source scope -list — List the debug (or specified) scope HDL source scope -list [start [end]] [scope] You can use ‘-’ for start and/or end line number.

ncsim> scope -list rgs_test.c1 1: `timescale 1 ns / 1 ns 2: 3: module clock 4: #( 5: parameter integer PERIOD = 20, 6: parameter integer COUNT = 9 7: ) 8: ( 9: output clk 10: ) ; 11: 12: reg start = 0; 13: initial start = #(PERIOD/2) 1; 14: initial start = #(PERIOD*9) 0; 15: 16: nand #(PERIOD/2) ( clk, clk, start ) ; 17: 18: endmodule

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Listing the Design Objects  scope -describe — Describe objects in debug (or specified) scope

scope -describe \ [-names] [-sort {name | kind | declaration}] [scope_name]

 describe — Describe specified objects

describe object [object ...] [-verbose] describe -power [-verbose] ncsim> describe vlog_bus[3] n(3).......signal : std_logic = '1' ncsim> describe vhdl_bus(3) n[3]......net (wire/tri) logic = St1

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Traversing the Design Debug commands accept hierarchical pathname arguments. The following command sets all list the same code: rgs_test

scope -set rgs_test.r1.d7

c1

scope -list

r1

m0

m4

d0

d4

m1

m5

d1

d5

scope -set rgs_test.r1

m2

m6

d2

d6

scope -list d7

m3

m7

d3

d7

scope -set rgs_test

scope -list r1.d7

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Listing the Drivers of an HDL Signal  scope -drivers — Display information about the drivers of HDL object(s)

scope -drivers [scope]

 drivers -active — List active drivers

drivers -active

 drivers -show — List all contributors to the value of each object

drivers [-show] object_name [object_name ...] \ [-effective] [-future] [-novalue] [-verbose]

 See example on following page...

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Example Listing HDL Drivers entity rgs is port ( q : out std_logic_vector (7 downto 0); data : in std_logic_vector (7 downto 0); clk : in std_logic; enb : in std_logic; rstn : in std_logic ); end rgs; ncsim> drivers :r1:rstn :r1:rstn...port : in std_logic = '0' '0' <- (:TEST) [File: rgs_test.vhd, Line: 25]

module rgs ( output [7:0] input [7:0] input input input

q , data, clk , enb , rstn ); ncsim> drivers rgs_test.r1.rstn rgs_test.r1.rstn...input net (wire/tri) logic = St0 St0 <- (rgs_test.r1) input port 5, bit 0 (./rgs_test.v:13)

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Getting Signal Values value — Display the value of simulation object(s) value [format_specifier] [pot_flow_specifier] object(s) Formats default to value of *_format variable set vhdl_format format

– (one of %b %d %h %o %v %x)

set vlog_format format

– (one of %b %c %d %e %f %g %h %o %s %t %v %x)

ncsim> value %b q UUUUUUUU – VHDL output 8'bxxxxzxxx – VLOG output

format — Format a string (standard Tcl command) format format_string [argument(s)] ncsim> puts "[time] [format "q=%s data=%s" [value %b q] [value %h data]]"

20 NS q=UUUUUUUU data=FF 20 NS q=8'bxxxxzxxx data=8'hff

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– VHDL output – VLOG output

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Forcing Signal Values  force — Force an object to a value or show active forces

force object_name [=] value [after time_spec [value after time_spec ...]] [release [keepvalue] time_spec] [repeat time_spec [cancel time_spec]] force -show [-quiet] ncsim> force rgs_test.r1.rtsn = 1'b0 ncsim> force –show rgs_test.r1.rtsn <- 1'h0 ... from TCL ncsim> force -show –quiet rgs_test.r1.rtsn You can also use scope -drivers to list all drivers, including currently active forces, on signals at the current HDL scope.  release — Release force set on object(s)

release [-keepvalue] object(s) ncsim> release rgs_test.r1.rtsn -keepvalue June 21, 2011

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Depositing Signal Values deposit — Deposit a value on a port, signal, or variable deposit object_name [=] value [after time_spec [value after time_spec ...]] [{relative | absolute}] [cancel 0] [constraint_mode constraint_name [=] {0 | 1}] [generic] [inertial] [rand_mode object_name [=] {0 | 1}] [release] [repeat period [cancel period]] [transport] ncsim> value %b rgs_test.r1.rtsn 1'bz ncsim> deposit rgs_test.r1.rtsn 0 ncsim> !-2 value %b rgs_test.r1.rtsn 1'b0

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Set Signal Values from Testbench Code: Verilog Standard Verilog provides testbench access to out of scope design signals:  assign (deassign) — Continuously assign an expression to a variable assign variable_lvalue = expression

deassign variable_lvalue assign rgs_test.fail = 0 ; deassign rgs_test.fail ;

 force (release) — Continuously force an expression to a variable or net force {net_lvalue | variable_lvalue} = expression

release {net_lvalue | variable_lvalue} force rgs_test.r1.rtsn = rgs_test.r1.rstn ; release rgs_test.r1.rtsn ;

Cadence Verilog also provides the $deposit system task:  $deposit — Deposit a non-persistent logic value onto a net or variable $deposit ( variable, value ) ; $deposit ( rgs_test.r1.rtsn, 0 ) ; June 21, 2011

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Set Signal Values from Testbench Code: Verilog (continued) For consistency, Cadence also provides Verilog counterparts of the VHDL utilities:  $nc_mirror — Mirror a Verilog wire or VHDL signal $nc_mirror ( "destination", "source" [,"verbose"] ) ; $nc_mirror ( "top.dest", "top.I1:src", "verbose" ) ;

 $nc_deposit — Deposit a value onto a Verilog net or VHDL signal $nc_deposit ( "source", "value" [,[time]" [,"[delay_type]" [,"verbose"]]]] ); $nc_deposit ( "top.I1:src", "11010101", "10 ns", "inertial", "verbose" ) ;

 $nc_force — Force a value onto a Verilog net or VHDL signal $nc_force ( "source", "value" [,"[after_time]" [,"[rel_time]" [,"[repeat_time]" [,"[cancel_time]" [,"verbose"]]]]] ) ; $nc_force ( "top.I1:src", "11010101", "", "", "", "", "verbose" ) ;

 $nc_release — Release a force $nc_release ( "source" [,"[keepvalue]" [,"verbose"]] ) ; $nc_release ( "top.I1:src", "keepvalue", "verbose" ) ;

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Monitoring Signal Value Changes with probe probe -screen — Probe object changes to the screen Use the probe -screen command to probe objects (not scopes) to the screen. The objects can include Verilog memories, memory ranges, and memory elements.

probe screen [format string] [redirect filename [append]] object(s) ncsim> probe -screen -format "%T %b %b %b %b" rstn load data q Created probe 1 ncsim> run 40 Time: 10 NS 1'b1 1'b1 8'b11111111 8'bx000zx00 Time: 20 NS 1'b1 1'b1 8'b11111111 8'bx111z111 Time: 30 NS 1'b1 1'b1 8'b00000000 8'bx111z111 Time: 40 NS 1'b1 1'b1 8'b00000000 8'b0000z000

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Monitoring Signal Value Changes with strobe strobe — Strobe object values to the screen You can have at most one strobe set at any given time. strobe {condition | object | time} spec formatobject_list [redirect filename [append]] strobe –delete strobe –help ncsim> strobe -condition {[value clk] == 1'b1} {load %b} data Setting up strobe condition - ’[value clk] == 1'b1’ ncsim> run 20 Time |load |data | -----------------------------110 NS |1'b1 |8'h0f | Ran until 120 NS + 0

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Manipulating Simulation Databases Use the database command to open, close, disable, or enable an SHM, VCD, or EVCD database, or to show information about it. This command defaults the options you most commonly use. For example, the database waves command opens the waves SHM database into the waves.shm directory and makes it the default SHM database if it is the first SHM database opened. database [open] name [shm] [default] [compress] [into dirname] [maxsize bytes] [event] [incfiles n] [incsize size] [statement] database [open] name vcd [default] [compress | gzip] [into filename] [maxsize bytes] [timescale timescale] [vcdmap map]

database [open] name evcd [direction] [default] [compress | gzip] [into filename] [maxsize bytes] [timescale timescale] database {close | disable | enable | show} glob_style_pattern database {change | setdefault} database [database ...] ncsim> database open waves shm default compress event into waves.shm maxsize 4194304 statement ncsim> database open waves evcd default into verilog.evcd maxsize 1048576 timescale ns Also see reference appendix

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Manipulating Simulation Probes Use the probe command to create, disable, enable, or delete a signal probe, or to show information about it. You can probe SystemC signals only to SHM. This command defaults the options you most commonly use. For example, the probe shm ports command probes ports of the current scope to the default SHM database, creating it if necessary. You need to specify the database name (or type) only if you have more than one open. The simulator will open default ncsim.shm, ncsim.vcd, or ncsim.evcd databases in the current directory if you probe to a database type that does not yet exist. probe probe probe probe

[-create] [zillions_of_options] objects_and/or_scopes {-delete | -disable | -enable} [glob_style_pattern ...] -save [filename] -show [-database database] [glob_style_pattern ...]

ncsim> probe -create -name p1 -all -depth to_cells -waveform –shm ncsim> probe -create -name p2 -ports -depth all -evcd simple ncsim> probe -screen -redirect probe.log -format "%b %h" clk cnt

Also see reference appendix

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Probe Signals from Testbench Code: Verilog SHM Cadence provides Verilog testbench capture of signal waveform data. The Simulation History Manager (SHM) is a proprietary database format. You can manipulate an SHM database with these Verilog system tasks: $shm_open ( ["filename"] ) ;

Open database. Optionally provide name. Database name defaults to waves.shm

$shm_probe ( [signals] ) ;

Probe signals. Optionally specify signals. Signals default to ports at current scope.

$shm_close ;

Close the database.

initial begin $shm_open(); $shm_probe(); end

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Cadence Verilog $shm_open Parameters $shm_open ("db_name", is_sequence_time, db_size, is_compression, incsize, incfiles); db_name

Database name defaults to waves.shm

is_sequence_time

Save multi-transition data (0,1) defaults to 0 (not)

database_size

Database size (bytes) defaults to unlimited

is_compression

Database compression (0,1) defaults to 0 (none)

incsize

Incremental database file size (MB) defaults to unlimited

incfiles

Incremental database file number defaults to unlimited

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Cadence Verilog $shm_probe Parameters $shm_probe [ ( { scope | spec } [ ,scope | ,spec ] ... ) ] ; Arguments are scope / spec pairs and you can omit the scope or the spec or both!  The scope argument defaults to the debug scope

 The spec argument defaults to probing ports

spec

what is probed

default

Ports of the specified scope

"S"

Ports of the specified scope and below, excluding library cells

"C"

Ports of the specified scope and below, including library cells

"A"

Add the "A" character to probe all signals in the specified scopes

"F"

Add the "F" character to probe objects in Verilog functions in the specified scopes

"M"

Add the "M" character to probe memories in the specified scopes

"T"

Add the "T" character to probe objects in Verilog tasks in the specified scopes

initial begin $shm_open("waves.shm"); $shm_probe("S",top.alu, "AC"); end June 21, 2011

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Probe Signals from Testbench Code: Verilog VCD The Verilog language provides testbench capture of signal waveform data. A Value Change Dump (VCD) file contains ASCII header information, variable definitions, and value change data. You can manipulate a VCD database with these Verilog system tasks: $dumpfile ( "filename" )

Open database. Optionally provide name. Standard default name is dump.vcd Cadence default name is verilog.dump

$dumplimit ( size )

Stop recording after size bytes

$dumpvars ( ... )

Select signals for recording (see next page)

$dumpoff

Stop recording

$dumpon

Start recording again

$dumpall

Checkpoint the values of all recorded signals

$dumpflush

Flush database to disk

initial begin $dumpfile(); // verilog.dump $dumpvars(); // current scope and down end June 21, 2011

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Verilog VCD Signal Selection with $dumpvars You can optionally provide $dumpvars with a levels argument and a list of scopes and variables. The levels argument applies to the subsequent scopes. $dumpvars [(levels [,list_of_scopes_or_variables])] You can provide no arguments, just the levels argument, or all arguments: Task Call

Depth / Scope

$dumpvars

all / all

$dumpvars ( 1 )

1 / current

$dumpvars ( 1, top.u1 )

1 / top.u1

$dumpvars ( 2, top.u2 )

2 / top.u2

$dumpvars ( 0, top.u3, top.u1.r0.q )

all / top.u3, top.u1.r0.q

initial begin $dumpfile("verilog.dump"); $dumpvars(0,top); end

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Probe Ports from Testbench Code: Verilog EVCD The Verilog language provides extended testbench capture of port data. An Extended Value Change Dump (EVCD) file contains ASCII header information, port definitions, and change data for port direction, strength, and value. You can manipulate an EVCD database with these Verilog system tasks: $dumpports ( scopes, filename )

Open database. Optionally provide scopes and name. Standard default name is dumpports.evcd

$dumpportslimit ( size, filename )

Stop recording after size bytes

$dumpportsoff ( filename )

Stop recording

$dumpportson ( filename )

Start recording again

$dumpportsall ( filename )

Checkpoint the values of all recorded signals

$dumpportsflush ( filename )

Flush database to disk

initial $dumpports(top.dut); // DUT scope to dumpports.evcd

See the slightly different Cadence $dumpports implementation on the next page.

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Probe Ports from Testbench Code: Cadence EVCD Cadence offers versions of only the $dumpports and $dumpports_close tasks. You can omit all or any arguments, but must use sufficient commas to correctly position any subsequent arguments. $dumpports ( scopes, filename, ID, flag )

Open database. Optionally provide arguments: Default scope is current (must not be top-level unit). Standard default name is dumpports.evcd Cadence default name is verilog.evcd ID is a returned integer file identifier (no default). Default flag is 0. flag bit 1: Keep losing value flag bit 2: Generate IEEE output flag bit 3: Compress with compress flag bit 3: Dump direction in node info flag bit 5: Compress with gzip

$dumpports_close ( ID )

Close the database

initial $dumpports(top.dut); // DUT scope to verilog.evcd June 21, 2011

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The SimVision Design Browser Window Open a SimVision Design Browser window by invoking simvision. In the Design Browser window, select and send objects to a Waveform display.

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The SimVision Waveform Window Or start with a SimVision Waveform window by invoking simvision -waves.

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Setting Breakpoints stop — Create, disable, enable, delete, or show breakpoints Use the stop command to create, disable, enable, delete, or show breakpoints of various kinds during your interactive session. Enter run to resume simulation. stop [-create] [options] stop -show [{stop_name | pattern} ...] stop {-delete | -disable | -enable} {stop_name | pattern} ...

ncsim> stop -object rstn -execute {force r1.rtsn = #rstn} Created stop 1 ncsim> run 20 NS + 0 (stop 1: rgs_test.rstn = 0) ./rgs_test.v:32 {rstn, load, data} = 10’b0_1_11111111; ncsim> value r1.rtsn 1’h0 ncsim> run 40 NS + 0 (stop 1: rgs_test.rstn = 1) ./rgs_test.v:33 {rstn, load, data} = 10’b1_0_11111111; ncsim> value r1.rtsn 1’h1 ncsim> stop -disable 1 Also see reference appendix June 21, 2011

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Managing Assertions assertion — Enable and disable assertions and control assertion logging Use the assertion command to control various PSL and SystemVerilog assertionbased verification features and VHDL assert messages.

assertion assertion assertion assertion assertion ncsim> ncsim> ncsim> ncsim> ncsim>

{off | on} [psl | vhdl] [options] logging [psl | vhdl] [options] simstop [options] summary [options] strict {on | off}

assertion assertion assertion assertion assertion

-off –all -logging -all -redirect assert.log –summary -final -redirect assert.log -simstop -severity failure :DUT -depth all –strict on

Also see reference appendix

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Running the Simulation run — Run the simulator Use the run command to start simulation or resume a previously halted simulation. run run run run run run run run run run run

–adjacent -clean -delta [cycle_spec] -next -phase -process –rand_solve -return -step -sync [-timepoint] [time_spec] [-absolute | -relative]

One HDL statement, staying in current process To a “clean” point where you can save To next or specified number of cycle(s) One HDL statement, stepping over calls To next phase of delta cycle Until current process suspends Solve current randomize() call, return status Until current subprogram returns One HDL statement, stepping into calls To next analog/digital sync point To or for some time

ncsim> run 20 ns Ran until 60 NS + 0 ncsim> run step Stepped to 60 NS + 0 June 21, 2011

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Getting the Simulation Time time — Display simulation time Use the time command to get current simulation time scaled as you specify, and to operate on time variables. time time auto time module time [10 | 100]unit -delta -nounit -operation op arg [arg] set display_unit display_unit

Display time using display_unit units Display time using units that make it integer Display time using current debug scope time scale Display time using specified units Include delta cycle count Omit time unit Return results of an operation Set default display unit (auto, module, [10 | 100]unit)

ncsim> time delta 10 NS + 0

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Using the Command History List history — Manage command history Use the history command to modify the number of commands the history mechanism will keep, to redo a specific previous command, and to substitute for parts of a previous command before re-executing it. The history command is a standard Tcl command. history keep n history redo {n | string} history substitute old_str new_str n

Set history size Redo a command (or use !n) Redo modified command

ncsim> history 1 database -open waves -into waves.shm 2 probe -create -name peek -shm r1 -all -depth all –waveform 3 probe -screen -format "%b %b %b %b" rstn load data q 4 run -timepoint 10 5 stop -object rstn -if {#rstn == 0} -delbreak 1 6 run 7 force rgs_test.r1.rtsn 0 8 stop -object rstn -if {#rstn == 1} -delbreak 1 9 run 10 force rgs_test.r1.rtsn 1 11 history ncsim> history redo 8 Created stop 3 June 21, 2011

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Executing a Command Script input — input a Tcl script file Use input or the simulator -input command line option to execute a script file. The simulator executes the command script upon entering the interactive mode. Assuming the command script contains: puts [format "Executed script at %s" [time -nounit]]

 If you invoke the simulator with the input option: The simulator enters interactive mode and echoes and executes the script:

ncsim top -input "script.tcl" ncsim> puts [format "Executed script at %s" [time -nounit]] Executed script at 0

 If you input the command script with input and continue the simulation: At the next interactive prompt the simulator echoes and executes the script:

ncsim> input script.tcl; run 10 Ran until 10 NS + 0 ncsim> puts [format "Executed script at %s" [time -nounit]] Executed script at 10 June 21, 2011

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Pausing a Command Script pause — Pause an input script Use the pause command to pause, resume, and abort input scripts. pause Pause an input script (not available at keyboard) pause –abort [n | all] Abort previous, stacked, or all paused scripts pause -resume Resume most recently paused script pause -status List file name and line number of paused scripts Assume the scripts # tcl1 puts "enter 1" pause puts "exit 1" # tcl2 puts "enter 2" pause puts "exit 2"

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Example interactive session ncsim> input tcl1 ncsim> puts "enter 1" enter 1 ncsim> pause ncsim (pause 1)> input tcl2 ncsim (pause 1)> puts "enter 2" enter 2 ncsim (pause 1)> pause ncsim (pause 2)> pause –status Macro 'tcl2' paused at line '3' (Current Macro) Macro 'tcl1' paused at line '3' ncsim (pause 2)> pause –abort ncsim (pause 1)> pause –resume ncsim> puts "exit 1" exit 1 ncsim> exit Incisive Enterprise Simulation training

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Checkpointing a Simulation  save — Save a snapshot of the current simulation state

save [-simulation] snapshot_name [-overwrite] ncsim> stop -object rstn -if {#rstn == 1} -delbreak 1 Created stop 1 ncsim> run 40 NS + 0 (stop 1: rgs_test.rstn = 1) ./rgs_test.v:64 {rstn, load, data} = 10'b1_0_11111111; @(negedge clk) expect('h00); ncsim> save -simulation rst_snap Saved snapshot worklib.rst_snap:v ncsim> stop -time 100000 ns -execute {save new_snap -overwrite} –continue Created stop 2

 restart — Restart simulation with a specified saved snapshot

restart {snapshot_name | -show} ncsim> restart new_snap  reset — Reset the simulation to its initial time-zero state

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Exiting the Simulation  exit — Exit the Tcl shell process

The exit command is a standard Tcl command extended for the simulator.

exit ncsim> exit

Entering Control-d twice consecutively from the interactive prompt also exits the Tcl shell process.

 finish — Finish the simulation session

Use the finish command to finish the simulation session and (1) optionally display simulation time and (2) optionally include resource usage. The simulator then automatically exits the Tcl shell. finish [0 | 1 | 2] ncsim> finish

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Miscellaneous Common Simulator Commands  alias — Set, unset, or show a Tcl command alias

The alias command is a standard Tcl command. alias [-set] alias_name alias_definition

alias -unset alias_name alias [alias_name] ncsim> alias -set go {run 10 ns; value sum}  call — Call a CFC function or -defined system task or system function

call [-predefined | -systf] name [arg(s)] ncsim> call {$myprinter} {"set value to "} 8’hc  help — Display help about simulator Tcl commands, functions, or variables

The help command is a standard Tcl command extended for the simulator. help [-brief] [command | all [command_options]] help {-functions | -variables} [name(s)] ncsim> help -brief all -enable

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Miscellaneous Common Simulator Commands (continued)  process — Identify processes currently executing or scheduled to execute

process [-current] process {-all | -next | -eot} max_count

ncsim> process -all 10  profile — Control profiling

profile [-clear] [-dump [-overwrite] [filename]] [-off | -on] ncsim> profile  status — Display resource (U time and memory) usage and simulation time

status ncsim> status  version — Display the version of the simulator

version ncsim> version

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Miscellaneous Verilog Simulator Commands: task task — Invoke a Verilog task task [-schedule] task_name(s)

ncsim> deposit top.task1.input1 1 ncsim> stop -object top.task1.output1 Created stop 1 ncsim> task top.task1 ncsim> run 1 NS + 1 (stop 1: top.task1.output1 = 1) ./test.v:3 begin output1<=#1 input1;end ncsim> value top.task1.output1 1'h1

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Summary You should now be able to use the command line interface to interact with the simulator.

This chapter examined debugging with the textual interface:  Examining and traversing the design  Reading and writing simulation objects  Monitoring signals

 Setting breakpoints and running the simulation  Capturing waveform data  Using the command history list  Executing commands from a script

 Saving, resetting, and restarting the simulation  Exiting the simulator  and more... June 21, 2011

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About Lab 5 This lab focuses on the simulator textual command interface. For this lab you compile, elaborate, simulate and debug a trivial RISC. data_e

data ld_ac clk rstn

accumulator (rgs) ac_out

ld_ir

instruction (rgs)

data

clk rstn

sel

[7:5] ir_out [4:0] opcode

ir_addr (operand)

ALU ld_pc

inc_pc alu_out

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zero

rstn

program pc_out counter (cnt)

MUX (smx)

rd addr memory wr (mem) ld_ir data ld_ac controller ld_pc (ctl) inc_pc halt data_e sel Incisive Enterprise Simulation training

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Debugging with the Graphical Interface Chapter 7

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Chapter Objective Objective:  To use the graphical interface to interact with the simulator

Module topics and where we are now:  Debugging with the graphical interface  SimVision Use Models  SimVision Windows

 Some Other SimVision Utilities  SomVision for Low Power

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Simvision Use Models Interactive Verification Environment  Invokes simulator engine with access to all components of Simvision

% ncsim –gui [-options] snapshot

Simulator && Simvision

Post-Processing Environment  Access all component of Simvision without simulator

% simvision simulation_database [-options] \

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terminate

–snapshot snapshot_name

snapshot Database

Simvision

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SimVision Windows The Cadence simulation analysis environment (SimVision) contains several primary windows and additional graphical tools, for example: Console



Properties

Expression Calculator

Design Browser

Source Browser

Assertion Browser

Waveform

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Schematic Tracer

Simulation Cycle Debug

Memory Viewer

Simcompare Manager

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Console Window Use the Console window to interact with the simulator and the SimVision simulation analysis environment.

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Properties Window Use the Properties window to examine and set properties.

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Design Search Sidebar Use the Design Search sidebar to search for design objects.

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Trace Signals Sidebar Use the Trace Signals sidebar to trace signal flow.

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Comparison Results Sidebar Use the Comparison Results sidebar to show comparison results.

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Design Browser Window Use a Design Browser window to browse the design hierarchy and objects.

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Source Browser Window Use a Source Browser window to browse your source code.

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Waveform Window Use a Waveform window to display probed signal value change data.

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Schematic Tracer Window Use a Schematic Tracer window to display signals as a schematic.

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Memory Viewer Window Use the Memory Viewer window to view the contents of a memory.

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Some Other SimVision Utilities Other training courses further describe these windows: Expression Calculator

Assertion Browser

Simulation Cycle Debug

Simcompare Manager

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Windows Use a window to display data in a customizable format.

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Expression Calculator Windows Use an Expression Calculator window to create and edit expressions of signals.

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Simulation Cycle Debug Tool Use the Simulation Cycle Debug tool to step through simulation cycles, stopping at each time point, delta cycle, simulation phase, or scheduled process.

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SimCompare Manager Tool Use the SimCompare Manager tool to compare two simulation databases.

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Browse Design Power Domains

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Browse F Source

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Display Probed Power Domain Information

PD group - shutoff expr -- expr signals - isolation group -- isolation expr --- expr signals -- isolation port(s) - retention group -- save expr --- expr signals -- restore expr --- expr signals -- retention element(s) note cross-hatched outputs!

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Trace Isolation and Shutoff Drivers

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Browse Power-Related Assertions

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Summary You should now be able to use the graphical interface to interact with the simulator

This chapter examined debugging with the graphical interface:  SimVision Use Models  SimVision Windows  Some Other Simvision Utilities  SimVision for Low Power

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About Lab 6 This lab focuses on the simulator graphical interface. The lab has three parts. Do as many parts as you have time for: 1. Briefly explore the U design you have been working on  In this lab you briefly explore the Console, Design Browser, Source Browser,

and Waveform windows. You do not “debug” the design.

2. Explore and debug another memory design  In this lab you use the Console, Design Browser, Source Browser and Waveform

windows to debug the testbench of another memory design.

3. Explore in depth the waveform display window  In this longer lab you practice using the features of the Waveform window.

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Introduction to Simulator Utilities Chapter 8

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Chapter Objective Objective:  To able to use the simulator utilities

Module topics:  Introduction to simulator utilitie

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cds_plat, cds_root, ncroot : Miscellaneous Utilities Use cds_plat in your scripts to get the platform {ibmrs, lnx86, sun4v, etc.}. %cds_plat sun4v

Use cds_root in your scripts to get the installation root of an executable. %cds_root -version $CDS: version 07.02 09/14/2007 08:45 (cat71sun) $ %cds_root ncsim /cds/INCISIV92/IUS92

Use ncroot in your scripts to get the installation root of cds_root itself. %ncroot /cds/INCISIV92/IUS92 June 21, 2011

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checkSysConf : Check System Configuration Use checkSysConf to check for required operating system patches. checkSysConf [-chrv] checkSysConf RELEASE [-d directory] [-ilq] [-p patch]

checkSysConf IUS9.2 checkSysConf IUS9.2 -p 119059

Interesting options include: -c Check data files for possible conflicts

-d Specify directory for patch data -h Display brief help -i Suppress informational output -l Display the platform/OS/release datafile -p Display Cadence products require this patch -q Run quietly; output only / FAIL -r Display releases ed by data directory -v Display tool version June 21, 2011

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hal: HDL Analysis Technology Use hal to analyze your design (also works for SystemC). hal [options] source(s) hal [options] [lib.]cell[:view] HAL checks the design for consistency, reusability, portability, semantic correctness, synthesizability, testability, and more. Interesting options include: -bb_list

Provide file of black-box design units to exclude

-[no]check Specify non-default list of categories / checks -check_palladium

Do acceleration policy checks

-clock_list

Provide file of clock inputs (for clock and DFT tests)

-lintpragma

Enable check control via embedded pragmas

-ncb_sortby

Send log file to NCBrowse utility

-read_tlf

Read synthesis libraries (need for some categories)

-read_lib

Read synthesis libraries (need for some categories)

-top

Specify a sub-hierarchy to analyze

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ncbrowse: Browse Log Files Use ncbrowse to browse log files. ncbrowse [options] [logFileName(s)] ncbrowse hal.log -report -

+W,INCSEL (./latches_tb.v, 58|8): 'a' missing from sensitivity list

Interesting options include: -environment <arg>

Specify ncbrowse settings file

-filter <arg>

Filter by {category, file, logfile, severity, tag, tool}=value

-format <arg>

Format by {%F %G %L %M %S %s %T}

-nodefaultenv

Not to use default ncbrowse settings

-report <arg>

Specify report name (suppresses GUI)

-rulefile <arg>

Specify a message category definitions file

-sortby <arg>

Sort by {category, file, logfile, severity, tag, tool}

-order <arg>

Order by {alpha, count} (use with sortby)

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The NCBrowse GUI You can alternatively do your browsing using the GUI.

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ncdc: Decompile a Snapshot Use ncdc to decompile a snapshot. ncdc [options] [lib.]cell[:view] ncdc worklib.top -output top -split -pragma

The utility by default writes decompiled output to stdout. Interesting options include: -information

List files referenced by decompiled code

-mangle

Mangle identifiers

-map Write file mapping mangled names to original names -nosdf

Do not write SDF files

-origfiles

Reconstruct original files and write script to compile/elaborate design

-output Specify output file -pragma

Preserve pragmas

-sdf <path:path>

Map original SDF pathnames to current pathnames

-split

Split VHDL and Verito separate files

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ncgentb: Generate a Testbench from EVCD Use ncgentb to create a testbench from an EVCD file. ncgentb -input filename -dut [lib.]cell[:view] [options] \ instancename

ncgentb dff_test.dff_i -input ncsim.evcd -dut dff -into vhdl

Interesting options include: -concurrent

Generate concurrent assignments

-dut <arg>

Specify required DUT unit name

-into <arg>

Specify testbench language {verilog vhdl}

-input <arg>

Specify required EVCD file name

-overwrite

Overwrite existing testbench

-script <arg>

Generate script to simulate testbench

-testbench <arg>

Output file (ncsim_tb.v, ncsim_tb.vhd)

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nchelp: Help with cds.lib, hdl.var and Message Codes Use nchelp to:

 Display libraries defined in a specific (or all loaded) cds.lib file(s)

Display variables defined in a specific (or all loaded) hdl.var file(s) nchelp [options] {-cdslib | -hdlvar} [file_name] nchelp -cdslib ~/cds.lib nchelp -hdlvar

 Obtain a description of tool message codes nchelp [options] {-all | tool_name} message_code nchelp ncvlog BADCLP nchelp ncelab CUVWSP You can alternatively just read the help message files in: /tools/inca/files/help

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Example Using the nchelp Utility

%ncvlog top.v -cdslib nosuch.cds -nocopyright ncvlog: *F,BADCLP: the -CDSLIB argument’s path nosuch.cds does not exist or is not readable. attempt to specify a cds.lib nchelp ncvlog BADCLP file that is not found ncvlog/BADCLP = The path specified for the -CDSLIB argument is invalid. Check that the specified path exists and is readable. %ncelab top -nocopyright attempt to elaborate a design drv u1 (out1); containing a dangling output port | ncelab: *W,CUVWSP (./top.v,2|5): 1 output port was not connected: ncelab: (./drv.v,1): out2 nchelp ncelab CUVWSP ncelab/CUVWSP = The indicated module instance does not specify a connection for each output port in the module port list. The specified output ports are left unconnected.

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ncls: List Library Objects Use ncls to list the derived objects stored in the library system. ncls [options] [lib.][cell][:view] ncls project_lib.top:module ncls top -library project_lib -view module Just enter the arguments to list all objects of one or all views of a specified cell in one or all libraries. Omitting the library and view lists all objects of the cell.  Object selection options:  -code (COD), -snapshot (SSS), -verilog (VST), -overlay (SIG), -systemc (SCD), -vhdl

(AST)

 Unit type selection options:  -architecture, -body, -configuration, -connect, -entity, -interface, -module, -package, -

program, -primitive

 Information selection options:  -command, -dependents, -lockinfo, -messages, -no_std_ieee, -release, -source [-

absolute_path], -time June 21, 2011

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Example Using the ncls Utility

%ncls -all –nocopyright module worklib.drv:module (VST) module worklib.drv:module (SIG) <0x5a85e48e> module worklib.dut:module (VST) module worklib.dut:module (SIG) <0x34683e01> module worklib.top:module (VST) module worklib.top:module (SIG) <0x01f0b280> module worklib.tst:module (VST) module worklib.tst:module (SIG) <0x638c9e1c> module worklib.tst:module (COD) <0x638c9e1c> snapshot worklib.top:module (SSS)

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nack: Pack a Library Use nack to pack or unpack a reference library or change its attributes. nack [options] library_name

You can tag it as addonly, database (simulator default), or readonly

Interesting options include: -addonly

Set access to add-only

-database

Set access to read/write

-readonly

Set access to read-only

-tmpdir <arg>

Specify temporary directory

-unlock

Unlock the library

-unpack

Unpack the library

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nrotect: Protect your Intellectual Property Use nrotect to protect all or portions of your HDL source code. nrotect [options] filename(s) nrotect source.vhd -autoprotect -extension pro -language vhdl  Use the -autoprotect option or place code to protect between the

pragma protect begin and pragma protect end pragmas.  You can specify the key owner, algorithm, and whether public or private, using a

parameters file or additional pragmas. Refer to the simulator documentation.

Interesting options include: -autoprotect

Protect everything in the input file(s)

-extension <arg>

Specify the output file extension {p}

-language <arg>

Specify the input file language {vlog vhdl}

-overwrite

Overwrite existing output files

-parameters <arg>

Specify a parameters file

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ncrm: Remove Library Objects Use ncrm to remove the derived objects stored in the library system. ncrm [options] [lib.]cell[:view] ncrm project_lib.top:module

Just enter the arguments to remove one or all views of a specified cell from one or all libraries. Omitting the library and view removes all versions of the cell.

Interesting options include: -library <arg>

Remove all elements of the specified library

-release <arg>

Remove code (COD) objects of specified hotfix

-snapshot

Remove only the snapshot (SSS) object

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ncsdfc: Compile SDF Use ncsdfc to compile and decompile SDF files. ncsdfc [options] filename

The ncsdfc utility by default writes the “filename.X” compiled SDF file and the “filename.sdfd” decompiled file.

Interesting options include: -decompile

Decompile an existing SDF file

-output <arg>

Specify output file name

-update

Recompile only if out-of-date

-worstcase_rounding

Truncate min delays, round up max delays

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ncshell: Generate a Foreign Model Shell Use ncshell to generate a shell for importation of foreign models ncshell -import language -into language [options] [lib.]cell[:view]

Interesting options include: Option

Description

Option

Description

-all

Shell for all known SWIFT

-import <arg>

{fmi, swift, systemc, verilog, verilog ams, vhdl}

-ams

Verilog-AMS model import

-into <arg>

{systemc, vhdl, verilog}

-analopts <arg>

Analyzer options

-list <arg>

File listing HDL src

-analyze <arg>

Analyze HDL src

-nocompile

Do not compile shell

-backward

Leapfrog/VXL shell

-noescape

No escaped VHDL id’s

-comp <arg>

Component file name

-package <arg>

Specify package name

-fmient

FMI entity

-shell <arg>

Specify shell name

-fmilib

FMI library

-scopts <arg>

Specify ncsc options

-generic

Include generics

-ulogic

Use unresolved logic

-view <arg>

Verilog view

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ncsuffix: Get the Library Version You can use the ncsuffix utility in two ways:  To find the library file suffix that the installed tools use, e.g.

You can use ncsuffix in a shell command to filter file names: ncsuffix {-all -ast -cod -pak -sig -sss -vst} [options] % set suffix = ‘ncsuffix -nocopyright -pak‘ % echo $suffix sun4v.174.pak

% ls worklib/*.$suffix worklib/inca.sun4v.174.pak

 To find the tool version that created the library ncsuffix -release [options] library_name(s) % ncsuffix -nocopyright -release worklib library worklib is compiled with the following versions 9.20-p007 June 21, 2011

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ncupdate: Update the Library Use ncupdate to update design units, snapshots, or libraries. ncupdate [options] [lib.]cell[:view]

Interesting options include: -cmdfile <arg>

Specify VHDL compile command file

-exclfile <arg>

Specify file of libraries to exclude from update

-exclude <arg>

Specify a library to exclude from update

-force

Force update of already up-to-date objects

-library

Update entire library

-norecompile

Do not recompile

-nosource

Do not check timestamps

-overwrite

Overwrite an already existing script

-script <arg>

Write script to do update (does not run it)

-show

Show update script

-unit

Update unit only (not snapshot)

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nmp: Map Between Namespaces Use nmp to obtain information about, and map names between, namespaces. nmp -version nmp {getSpaceNames | getAllSpaceNames} nmp isLegalName spaceName identifier nmp mapName fromSpaceName toSpaceName identifier This example determines whether the proposed name is a legal Verilog name. nmp isLegalName Verilog '$myName' illegal This example maps an escaped VHDL name to the Verilog namespace. nmp mapName VHDL Verilog '\$myName\' \$myName This example maps an escaped Verilog library name to the file system namespace. nmp mapName Verilog Filesys '\u-lib ' u#2dlib June 21, 2011

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shellgen: Generate an OMI Shell Use shellgen to generate a VHDL or Verilog shell of an OMI-compliant model. shellgen -b bootstrap_file [options]

Interesting options include: -b <arg>

Specify vendor-provided model manager bootstrap file

-l <arg>

Constrain shell generation to the specified library

-m <arg>

Constrain shell generation to the specified model

-nomm_objext

Generate mm_object attribute value without extension

-nomm_path

Generate mm_object attribute value as empty string

-o <arg>

Specify the shell file name

-pli, -verilog, -vhdl

Specify the shell file type

-r

Overwrite an existing shell file if necessary

-unresolved

Use unresolved port types in VHDL shells

+manager_opt[=val]

the model manager its own vendor-defined options

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simcompare: Compare Waveform Databases Use simcompare to compare waveform databases. simcompare [options] [[ref_database] test_database] simcompare -report report.log ref.trn test.trn Interesting options include: -checkstrength Also compare signal strength -input file

Input commands from file and exit when done

-maxerrors n

Limit maximum reported errors per comparison

-report file

Report to file instead of stdout

-restore file

Restore comparison state

-save file

Save comparison state

-sequencetime Also compare zero-delay transitions -tcl

Enter interactive mode

-totalerrors n

Limit maximum total reported errors

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Simcompare Commands Command

Description

translate [-force] dbname_in [dbname_out] Translate VCD to SST2 database name pathname [-shift time] golden pathname test pathname

Define a database Define “golden” database Define “test” database

threshold name d1(a1) [...dN(aN)]

Define an analog-to-digital values map

threshold ttl St0(<0.8) StX(0.8=2.0) St1(>2.0)

sequencetime [on | off]

To include zero-delay transitions

statemap name \ testState1 testState2 [...testStateN] \ refState1:1 {1|0} [...{1|0}] \ refState2:{1|0} 1 [...{1|0}] \ ... [refStateN:{1|0} {1|0} ... 1]

Define a reference-to-test state map

statemap ignoreX 01ZX 0:1000 1:0100 Z:0010 X:1111

continued...

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Simcompare Commands (continued) Command

Description

clkdef name clkexpr [options]

Define a comparison clock

compare [golden [test] [options]]

Define an absolute comparison

clkcompare [clkexpr valexpr] [options]

Define a clocked comparison

stability clkexpr valexpr [options]

Define a stability check

report [comparisons] [options]

Generate a full or summary report

save filename restore filename

Save comparison state to a file Restore comparison state from a file

Following pages more fully describe the comparison and check commands.

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Simcompare Command Options: Common Common Option

Description

-append

Append to report

-bitblast

Bit blast buses for comparison

-[no]checkstrength

Override invocation option and command

-detail [full | summary]

Override default detail for command

-start time -end time

Start check End check

-maxerrors n

Override invocation option and command

-name string

Name the definition

-output file

Redirect output to file

-[no]sequencetime

Override invocation option and command

-[no]stdout

Suppress or force stdout

-when expr

Condition the check

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Performing an Absolute Comparison The compare command does an absolute comparison. compare [golden [test] [options]] Options for compare command

Description

-alltypes

Show all checks and comparisons

-signals -ports -allvars

Compare signals (default) Also compare ports Compare ports and signals

-depth level

Limit compare depth (0=all)

-ignoreundefined {golden | test | both } -ignoreunknown {golden | test | both }

Ignore fully undefined (U) signals Ignore fully unknown (X) signals

-neg n -pos n -tol n

Specify negative tolerance (0) Specify positive tolerance (0) Specify symmetric tolerance (0)

-shift[g|t] time

Shift transitions in golden, test, or both

-statemap map

Use specified state map

-threshold[g|t] map

Use specified threshold map

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Defining a Comparison Clock The clkdef command defines a clock for clocked comparisons and stability checks. clkdef name clkexpr [options] Options for clkdef command

Description

-bothedge -negedge -posedge -edge edge

Active edge is both Active edge is negative Active edge is positive Active edge is specified edge

-clkshift time

Shift the clock expression

-setup[g|t] time -hold[g|t] time

Setup time in golden, test, or both Hold time in golden, test, or both

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Performing a Clocked Comparison The clkcompare command does a clocked comparison. clkcompare [clkexpr valexpr] [options] You can optionally utilize a defined clock.

Options for clkcompare command

Description

-bothedge -negedge -posedge -edge edge

Active edge is both Active edge is negative Active edge is positive Active edge is specified edge

-clkshift time -shift time

Shift the clock expression Shift the value expression

-clkt expr -valt expr

Specify an alternative test clock Specify an alternative test expression

-clkthreshold[g|t] map -threshold[g|t] map

Specify threshold map for clock Specify threshold map for values

-setup[g|t] time -hold[g|t] time

Setup time in golden, test, or both Hold time in golden, test, or both

-statemap map

Specify state map

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Performing a Stability Check The stability command does a stability check. stability clkexpr valexpr [options] You can optionally utilize a defined clock.

Options for stability command

Description

-bothedge -negedge -posedge -edge edge

Active edge is both Active edge is negative Active edge is positive Active edge is specified edge

-clkshift time -shift time

Shift the clock expression Shift the value expression

-clkthreshold map -threshold map

Specify threshold map for clock Specify threshold map for values

-setup time -hold time

Setup time in golden, test, or both Hold time in golden, test, or both

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Example Comparisons g::top.s1

database ref.trn database tst.trn compare top.s1 \ -shift -30 -tol 10

<- shift

t::top.s1 -tol+ neg

golden ref.trn test tst.trn compare top.s1 \ -neg 25ns -pos 15ns \ when "!rst"

pos

g::top.s1

t::top.s1 g::rst

database bar tst.trn database foo ref.trn clkdef CLK foo::top.clk \ -negedge golden foo test bar clkcompare CLK top.s1 \ -setup -15ns -hold 45ns June 21, 2011

setup foo::top.clk

hold

negedge ->

foo::top.s1 bar::top.s1

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simvisdbutil: SimVision Database Utility Use simvisdbutil to translate waveform databases in batch mode. simvisdbutil [-options] filename(s)

You can translate VCD, EVCD, HSPICE, Nutmeg, Epic, and Qsim to SST2. You can translate SST2 to VCD or CSV. The simvisdbutil utility by default creates local “SST2 .dsn” and “SST2 .trn” files.

Interesting options include: -compress

Compress the SST2 output

-{csv|shm|sst2|vcd}

Output the specified format

-output <arg>

Place output in specified file: filename.{csv|shm|trn|vcd}

-range start:end

Include the specified range

-overwrite

Overwrite an existing output file

-sequence

Include sequence time information

-signal <arg>

Include the specified signal

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Summary You should now be able to use these simulator utilities:  cds_plat

 ncdc

 nrotect

 ncsuffix

 cds_root

 ncexport

 ncrelocate

 ncupdate

 checkSysConf

 ncgentb

 ncrm

 nmp

 hal

 nchelp

 ncroot

 shellgen

 ncsc_env_check

 ncls

 ncsdfc

 simcompare

 ncbrowse

 nack

 ncshell

 simvisdbutil

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About Lab 7 In this lab you:  Use the HAL utility to analyze the RISC design of lab 5  Use the NCBrowse utility to examine the HAL log file  Use the HAL definition file editor to examine the default definitions

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Annotating SDF Timing Chapter 9

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Chapter Objective Objective:  To annotate timing information

Module topics:  Annotating SDF timing  Briefly describe the purpose of annotation  Understand an SDF timing data file

 Work around SDF annotation issues  Annotate SDF timing data

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Describing Timing Annotation A silicon vendor simulation library typically contains estimated intrinsic timing. For accurate timing simulation you need additional data:  Drive strength  Interconnect parasitics  Total load  Environmental factors  process  temperature  voltage

You also need to simulate fast clock with slow data and slow clock with fast data. Most event simulators cannot directly do this.

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Timing Data Flow Design Capture

Floorplan Refinement

Delay Calculation

Delay Calculation

Functional Simulation

Clock Insertion, Reoptimization

In Place Optimization

SPF Data

Floorplanning

Global Routing, Reoptimization

ECO Routing

Scan Insertion

Final Routing

Design Rule Checking

Back-End Flow Synthesis

Parasitic Extraction

Placement

SPF Data

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219

Delay Calculators Two major categories of delay calculators exist:  Delay calculators embedded in the tools  Synthesis tools

 Static timing analysis tools

 Custom delay calculators  -defined  Vendor-supplied

Delay calculators can generate SDF data, or directly annotate timing data using the Application Programming Interface (API).

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Understanding an SDF File The SDF provides a tool-independent, uniform way to specify timing data. This section presents an example SDF file and then explains the:  SDF header data  SDF cell timing data  SDF cell labels  SDF cell delays  SDF cell timing checks

 SDF cell timing environment

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Example SDF File (DELAYFILE (SDFVERSION "3.0") (DESIGN "system") (DATE "Thu Nov 5 14:10:03 EST 2009") (VENDOR "Cadence") (PROGRAM "delay_calc") (VERSION "09.20-p007") (DIVIDER /) /*hierarchical divider */ (VOLTAGE 4.5:5.0:5.5) (PROCESS "worst") (TIMESCALE 1ns) /* delay time units */ (CELL (CELLTYPE "system") (INSTANCE block_1) /* top-level blocks */ (DELAY (ABSOLUTE (INTERCONNECT D1/z P3/i (.155::.155) (.130::.130))))) (CELL (CELLTYPE "INV") (INSTANCE *) /* all instances of "INV" */ (DELAY (INCREMENT (IOPATH i z (.345::.348) (.325::.329))))) (CELL (CELLTYPE "OR2") (INSTANCE B1/C1) /* this instance of "OR2" */ (DELAY (ABSOLUTE (IOPATH i1 z (.300::.300) (.325::.325)) (IOPATH i2 z (.300::.300) (.325::.325))))) )

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Understanding SDF Header Keywords An SDF file starts with a header (most of which is merely documentation): Keyword

Status

Format

Default

SDFVERSION

Required

qstring

none

DESIGN

Document

qstring

none

DATE

Document

qstring

none

VENDOR

Document

qstring

none

PROGRAM

Document

qstring

none

VERSION

Document

qstring

none

DIVIDER

Optional

hchar

‘.’

VOLTAGE

Document

real | rtriple

none

PROCESS

Document

qstring

none

TEMPERATURE

Document

real | rtriple

none

TIMESCALE

Optional

number unit

1 ns

(DELAYFILE (SDFVERSION "4.0") (CELL ...) ... ) syntax

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Understanding SDF Cell Timing Keywords A CELL keyword identifies a design subscope and the timing data to apply there: Keyword

Status

Format

Default

CELL

Required

syntax

none

CELLTYPE

Required

qstring

none

INSTANCE

Required

see notes

see notes

LABEL

Optional

lbl_type

none

DELAY

Optional

deltype

none

TIMINGCHECK

Optional

tchk_def

none

TIMINGENV

Optional

te_def

none

(CELL (CELLTYPE type) (INSTANCE scope) (LABEL ...) (DELAY ...) (TIMINGCHECK ...) (TIMINGENV ...) ... )

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Understanding SDF Cell Label Keywords A LABEL keyword replaces or adds delay values to labels: Keyword

Specifies

ABSOLUTE

Absolute (replaced) delay values

INCREMENT

Incremental (added) delay values

(LABEL (ABSOLUTE (name delays) ... ) (INCREMENT (name delays) ... ) ... )

syntax

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Understanding SDF Cell Delay Keywords A DELAY keyword applies cell and net delay and pulse reject and error values or ratios: Keyword

Specifies

ABSOLUTE

Absolute delay replaces any existing delay

INCREMENT

Incremental delay adds to any existing delay

PATHPULSE

Path pulse control reject and error values

PATHPULSEPERCENT

Path pulse control reject and error ratios (percent)

DEVICE

Cell delay to a specific (or all) cell output(s) (or inout(s))

IOPATH

Cell delay from a specific cell input (or inout) to a specific cell output (or inout)

RETAIN

Time for IOPATH to maintain previous state

COND

Conditional cell delay

CONDELSE

Default cell delay (applies only to matching COND)

NETDELAY

Net delay from all sources of the net to all loads of the net

PORT

Net delay from all sources of the net to a specific input (or inout) port

INTERCONNECT

Net delay from a specific output (or inout) port to a specific input (or inout) port syntax

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Annotating Cell Delay In the SDF file, annotate cell delay with:  The DEVICE keyword to specify the intrinsic delay of a cell, gate, or port

instance  This specifies min:typ:max delay for rise, fall, and turn off edges ( DEVICE U1 (7:8:9) (1:2:3) (4:5:6) )  This specifies min:typ:max delay, reject, and error for all edges ( DEVICE U1 ( (7:8:9) (1:2:3) (4:5:6) ) )

 The IOPATH keyword to specify the delay from an instance input to an instance

output  This specifies min:typ:max delay for rise, fall, and turn off edges ( IOPATH INA OUTA (7:8:9) (1:2:3) (4:5:6) )  This specifies min:typ:max delay, reject, and error for all edges ( IOPATH INA OUTA ( (7:8:9) (1:2:3) (4:5:6) ) )

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Example IOPATH Delay Specification Syntax /* 1-delay expressions, with and without reject and error limits */ (IOPATH (IOPATH (IOPATH (IOPATH

p_in p_in p_in p_in

p_out (delay_triple) ) p_out ((delay_triple) (reject_triple) )) p_out ((delay_triple) ( ) (error_triple))) p_out ((delay_triple) (reject_triple) (error_triple)))

/* 2-delay expressions, with and without reject and error limits */ (IOPATH p_in p_out

(rise_triple) (fall_triple) (IOPATH p_in p_out ((rise_triple) ((fall_triple) (IOPATH p_in p_out ((rise_triple) ((fall_triple) (IOPATH p_in p_out ((rise_triple) ((fall_triple)

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) (reject_triple) (reject_triple) ( ) ( ) (reject_triple) (reject_triple)

Incisive Enterprise Simulation training

) )) (error_triple)) (error_triple))) (error_triple)) (error_triple)))

228

Annotating Net Delay In the SDF file, annotate net delay with:  The PORT keyword to specify the delay of all interconnections to an input port  This specifies min:typ:max delay for rise, fall, and turn off edges ( PORT IN (7:8:9) (1:2:3) (4:5:6) )  This specifies min:typ:max delay, reject, and error for all edges ( PORT IN ( (7:8:9) (1:2:3) (4:5:6) ) )

 The INTERCONNECT keyword to specify the delay from an instance output to

an instance input  This specifies min:typ:max delay for rise, fall, and turn off edges ( INTERCONNECT a.OUT b.IN (7:8:9) (1:2:3) (4:5:6) )  This specifies min:typ:max delay, reject, and error for all edges ( INTERCONNECT a.OUT b.IN ( (7:8:9) (1:2:3) (4:5:6) ) )

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Example INTERCONNECT Delay Specification Syntax /* 1-delay expressions, with and without reject and error limits */ (INTERCONNECT (INTERCONNECT (INTERCONNECT (INTERCONNECT

A.out A.out A.out A.out

B.in (delay_triple) ) B.in ((delay_triple) (reject_triple) )) B.in ((delay_triple) ( ) (error_triple))) B.in ((delay_triple) (reject_triple) (error_triple)))

2-delay expressions, with and without reject and error limits */ (INTERCONNECT A.out B.in

(rise_triple) (fall_triple) (INTERCONNECT A.out B.in ((rise_triple) ((fall_triple) (INTERCONNECT A.out B.in ((rise_triple) ((fall_triple) (INTERCONNECT A.out B.in ((rise_triple) ((fall_triple)

June 21, 2011

) (reject_triple) (reject_triple) ( ) ( ) (reject_triple) (reject_triple)

Incisive Enterprise Simulation training

) )) (error_triple)) (error_triple))) (error_triple)) (error_triple)))

230

Understanding SDF Cell Timing Check Keywords A TIMINGCHECK keyword specifies minimum or maximum limits for the time between transitions of two signals or two transitions of the same signal: Keyword

Stamp

Check

Value

Limit

SETUP

port 1

port 2

Positive

Min

HOLD

port 2

port 1

Positive

Min

SETUPHOLD

port 1,2

port 2,1

Signed

Min

RECOVERY

port 1

port 2

Positive

Min

REMOVAL

port 2

port 1

Positive

Min

RECREM

port 1,2

port 2,1

Signed

Min

SKEW

port 1,2

port 2,1

Signed

Max

BIDIRECTSKEW port 1,2

port 2,1

Positive

Min

WIDTH

port

port

Positive

Min

PERIOD

port

port

Positive

Min

NOCHANGE

port 2,1

port 1,2

Signed

Min

syntax

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Understanding SDF Cell Timing Environment Keywords A TIMINGENV keyword associates constraint values with critical paths in the design and provides information about the timing environment in which the circuit will operate. Constructs in this subclause are used for forward annotation to design implementation tools. Keyword

Specifies

PATHCONSTRAINT

Max path delay

PERIODCONSTRAINT

Max clock period

SUM

Max sum of multiple path delays

DIFF

Max difference between two path delays

SKEWCONSTRAINT

Max clock skew

ARRIVAL

Input port arrival time

DEPARTURE

Output port departure time

SLACK

Input port available slack

WAVEFORM

Clock waveform syntax

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Working Around Annotation Issues This section individually examines the following annotation issues:  SDF standard annotation issues  Language-specific annotation issues  Tool-related annotation issues  Simulator-specific annotation issues

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Working Around SDF Standard Annotation Issues Here are some general rules that you should be aware of:  Each SDF version reflects significant changes  Cadence defined SDF version 1.0

 OVI defined SDF versions 2.0, 2.1, 3.0  IEEE std. 1497-2001 defines SDF version 4.0  IEEE std. 1076.4-2000 (VITAL) s SDF version 4.0

 The annotator must apply SDF data in file order  Subsequent LABEL, TIMINGCHECK, TIMINGENV replace previous  Subsequent ABSOLUTE delays replace previous delays  Subsequent INCREMENT delays add to previous delays

 The annotator must apply cell path data only to existing constructs  Edge-qualified SDF cell paths do not map to unqualified cell paths  Conditional SDF cell paths do not map to unconditional cell paths

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Working Around Language-Specific Annotation Issues The IEEE std. 1076.4-2000 (VITAL) s a subset of SDF 4.0:  No for simultaneous annotation of min:typ:max values  Not sensitive to character case  No for PATHPULSE, PATHPULSEPERCENT, NETDELAY  No for escape characters

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Working Around Tool-Related Annotation Issues Here are some tool-related issues that you should be aware of:  The SDF escapes only individual identifier characters  The SDF allows a port to be an internal node  Annotators can convert INTERCONNECT delay to PORT delay  Annotators can ignore INTERCONNECT delay

 Annotators must attempt to apply DEVICE delays to cell timing paths  If unsuccessful, must apply to all primitives driving output port

 Simulation tools do not use TIMINGENV data  Not all annotators use negative values  Shall substitute 0 in ABSOLUTE clauses  May substitute 0 in INCREMENT clauses

 Simulators typically do not use negative delay

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Working Around Simulator-Specific Annotation Issues These are some simulator-specific issues that you should be aware of:  Simulator handling of mixed-language INTERCONNECT  Does not annotate INTERCONNECT data to mixed-language bidirectional

interconnect

 Simulator handling of mixed-language INTERCONNECT path pulse controls  s pulse controls for interconnect paths that terminate in a Verilog partition

 Simulator handling of missing INTERCONNECT  For Verilog — Converts to PORT delays  For VHDL — Ignores missing INTERCONNECT

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Annotating SDF Data with Incisive Simulators This section discusses:  Preparing the optional SDF configuration file  Preparing the SDF command file  Compiling SDF files with ncsdfc  Annotating SDF data  Annotating Verilog with $sdf_annotate

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Preparing the Optional SDF Configuration File The optional SDF configuration file filters SDF timing data prior to annotation. It can contain keywords to control how the data is used (default in bold):  TIMING_KEYWORD = IGNORE;

 SCALE_TYPE = [ FROM_MINIMUM | FROM_TYPICAL | FROM_MAXIMUM |

FROM_MTM ];  SCALE_FACTORS = 1.0:1.0:1.0;  MTM = [ MINIMUM | TYPICAL | MAXIMUM | TOOL_CONTROL ];

 MODULE definition_name // Verilog ONLY { SCALE_TYPE = [ FROM_MINIMUM | FROM_TYPICAL | FROM_MAXIMUM | FROM_MTM ]; SCALE_FACTORS = 1.0:1.0:1.0; MTM = [ MINIMUM | TYPICAL | MAXIMUM ]; MAP_INNER = hierarchical_instance_name; [ (sdf_timing_path) = IGNORE; ] [ | (sdf_timing_path) = ADD { (hdl_timing_path); ...; } ] [ | (sdf_timing_path) = OVERRIDE { (hdl_timing_path); ...; } ] }

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Preparing the SDF Command File Create an SDF command file to control the annotation process: Keyword

Example

Specifies

COMPILED_SDF_FILE =

"u.sdf.X",

Compiled SDF file name

SCOPE =

m1,

Module instance path name

CONFIG_FILE =

"u_sdf.cfg",

Configuration file name

LOG_FILE =

"u_sdf.log",

Log file name

MTM_CONTROL =

"MINIMUM",

MTM control

SCALE_FACTORS =

".201:1.01:3.01",

Scale factors

SCALE_TYPE =

"FROM_MINIMUM";

Scale type

The COMPILED_SDF_FILE keyword is required. You can omit all other command file keywords. The MTM_CONTROL, SCALE_FACTORS, and SCALE_TYPE keywords in the command file override those in the configuration file. You can annotate multiple units simultaneously. Just specify another SDF file and scope. Enter the following statements in any order. Use commas to separate statements and use a semicolon after the last statement of the file. to use the period (‘.’) hierarchy divider for Verilog scopes (i.e. top.dut.sub) and the colon (‘:’) hierarchy divider for VHDL scopes (i.e. :dut:sub).

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Compiling SDF files with ncsdfc Compile the SDF file with ncsdfc: ncsdfc [options] filename.sdf ncsdfc -worstcase_rounding timing.sdf

Interesting options include: -decompile

Decompile the specified SDF files

-output <arg>

Redirect the compiled SDF output

-update

Recompile only if necessary

-worstcase_rounding

Round min delays down, max delays up

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Annotating SDF Data Provide the SDF command file to the elaborator: ncelab design_unit [-intermod_path] -sdf_cmd_file filename ncelab top -intermod_path -sdf_cmd_file u_sdf.cmd

ncelab top -sdf_cmd_file u_sdf.cmd -sdf_cmd_file alu_sdf.cmd

These annotation-specific elaborator options affect both VHDL and Verilog: Common Option

Description

-sdf_cmd_file filename

Provide an SDF command file

-intermod_path

Enable multisource interconnect delays

-no_sdfa_header

Suppress display of SDF header information

-sdf_no_warnings

Suppress display of SDF annotator warnings

-sdf_precision precision

Specify maximum precision for SDF data

-sdf_verbose

Display detailed SDF annotator activity

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Elaborator Annotation Options: Verilog Option

Description

-anno_simtime

Allow runtime API annotation

-caint

Allow INTERCONNECT annotation across continuous assignments

-noautosdf

Disable automatic $sdf_annotate SDF annotation

-sdf_nocheck_celltype

Suppress validation of cell type declaration

-sdf_nopulse

Ignore SDF path pulse reject and error data

-sdf_simtime

Allow runtime $sdf_annotate SDF annotation

-sdf_spep

Use specify block PATHPULSE parameters

-sdf_worstcase_rounding

Round min delays down, max delays up

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Automatically Annotating Verilog with $sdf_annotate You can annotate the Verilog portions of your design with the $sdf_annotate built-in system task. Task arguments correspond to command file entries. Only the SDF file name argument is required: $sdf_annotate ( "sdf_file", "module_instance_path_name", "configuration_file", "log_file", "mtm_spec", "scale_factors", "scale_type" ) ; $sdf_annotate ( "timing.sdf", , , "sdf.log" ) ;

The elaborator by default executes any $sdf_annotate system tasks unambiguously scheduled to execute at simulation time 0. That means:  You cannot place the $sdf_annotate system task in an always block  You cannot precede the $sdf_annotate system task with a timing control  You cannot place the $sdf_annotate system task in a case, for, repeat. or while

 You cannot place the $sdf_annotate system task in an if statement if the conditional

expression is not statically computable

Otherwise use sdf_simtime to postpone annotation until simulation time. June 21, 2011

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Summary You should now be able to annotate timing information

This chapter described annotating SDF timing:  Briefly explained the purpose of annotation  Described an SDF timing data file  Exposed SDF annotation issues  Instructed annotation of SDF timing data

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About HDL Lab 8 In this lab, you annotate design timing data:  Compile SDF data with ncsdfc  Prepare an SDF command file  Annotate and simulate a design  Analyze timing violations

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Conclusions and Next Steps Chapter 10

June 21, 2011

Course Summary You should now be able to simulate your Verilog design using an Incisive simulator.

Module 1 described the fundamentals for doing Incisive simulation:  Briefly described Incisive simulation  Described setting up your environment for Incisive simulation  Described compiling, elaborating, and simulating your design and testbench  Described debugging your design with the textual

Module 2 explored advanced Incisive simulation topics:  Described debugging your design with the graphical interfaces

 Utilizing additional simulation-related utilities  Annotating SDF timing data to the HDL portions of your design

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Congratulations!

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Next Steps This training examined Incisive Verilog simulation:  Fundamentals

 Advanced topics

 Setup

 Other utilities

 Compile

 Mixed-language

 Elaborate

 Timing annotation

 Simulate

 Application programming

 Debug

 Advanced SystemC features

Cadence offers much more training related to Incisive simulation:  Languages (basic and adv.)

 Tools

 Methodology

 e

 Assertions

 Verification planning

 SystemC

 Coverage

 Verification management

 VHDL

 Power

 Open Verification Methodology

 Verilog

You can continue your training in these subjects: http://www.cadence.com/Training/

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Incisive Functional Verification Courses Design & Verification

Core

Experienced

Expert

XL SystemVerilog Advanced Verification Using OVM

XL SystemVerilog Verification Using Module-Based OVM

SystemVerilog Language

XL

System C/C++

SystemVerilog Advanced SVA and Formal Verification

Advanced PSL and Formal Verification

Functional Formal Verification

Verification with PSL

SystemVerilog Assertions

XL

Transaction Level Modeling

XL Incisive Simulation of PSL Assertions

Verification with VHDL

L

VHDL for Verilog s

L

Verilog Language and Application

Verilog for VHDL s

L

VHDL Language & Application

XL Incisive SystemC, VHDL, and Verilog Simulation

L

Deg with VHDL

SystemC Verification (SCV)

C++ Language

SystemC Fundamentals

XL

L

Continued

Also available as an Internet Learning Series course L, XL, GXL Denotes tiers of Cadence products

June 21, 2011

Incisive Enterprise Simulation training

251

Incisive Functional Verification Courses (continued)

Core

Experienced

Expert

Verification

Specman Elite Advanced Verification

XL

Specman Elite Basics for Environment Developers

XL

XL Specman Elite Basics for Environment s

Metric-driven Verification

Scripting

XL Verification Planning Using Enterprise Planner

Low Power Simulation

XL

Incisive Comprehensive Coverage`

XL

Intoduction to Metric-Driven Verification Workshop

Perl for EDA Engineering

Tcl Scripting for EDA + Intro to Tk

XL Incisive SystemC, VHDL, and Verilog Simulation

Also available as an Internet Learning Series course L, XL, GXL Denotes tiers of Cadence products

June 21, 2011

Incisive Enterprise Simulation training

252