Aspire 5253 (compal La-7092p Rev.1.0) 5l4u6f

[email protected]

1

1

2

2

C1006 0.1U_0402_16V4Z

Change 0603 size For DVT

2

100K_0402_5%

+LCDVDD

2

Q83 SSM3K7002F_SC59-3

1

1 DISO@ 2 R964 0_0402_5%

<18> VGA_ENVDD

D

2 G 3

<5> APU_ENVDD

C670 0.047U_0402_16V7K

AO3413L_SOT23-3 Q82 1

1

2

2 D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

G1 G2 G3 G4 G5 G6

SM010014520 3000ma 220ohm@100mhz DCR 0.04

W=60mils

1

1

2

2

<5> APU_ENBKL

R156 1 UMA@ 2

0_0402_5%

B+ 2 L113 1.2UH_1127AS-1R2N_2.4A_30% R419 1 @ 2 0_0805_5%

ENBKL <31>

1

R426 1

@

1 R157

2 100K_0402_1% +3VS

2 0_0805_5%

C674 68P_0402_50V8J

EMI request for MP

1 R484 C1007 2

1 220P_0402_50V7K INVT_PWM

C679 2

1 220P_0402_50V7K DISPOFF#

2 1 10K_0402_5% R485

INVT_PWM DISPOFF# I2CC_SCL I2CC_SDA

@ 2 +LCDVDD R841

1 0_0603_5%

+LCDVDD D

W=60mils

+3VS

DAC_BRIG <31>

TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+

R862 2

@

1 0_0402_5%

LOCAL_DIM <31>

R860 2

@

1 0_0402_5%

COLOY_ENG_EN <31>

+3VS USB20_N5 <14> USB20_P5 <14>

C

D15 @ 6 +LCDVDD

Place closed to JLVDS1

2 0_0402_5%

1

<31> BKOFF#

+LCDVDD_L

@ R483 10K_0402_5%

5

+3VS

1 220P_0402_50V7K DAC_BRIG

C677 2

+INVPWR_B+

IPEX_20143-040E-20F CONN@

2

C673 680P_0402_50V7K

+INVPWR_B+ L2 FBMA-L11-201209-221LMA30T_0805 2 1 L1 FBMA-L11-201209-221LMA30T_0805 2 1

0_0402_5%

1

C

<19> VGA_ENBKL

R1097 1 DISO@ 2

W=60mils

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

DISPOFF#

2

1

C671

1

2

10U_0603_6.3V6M

2

CH2

Vp

Vn

3

USB20_N5

2

C672 USB20_P5

RB751V_SOD323 D4 @

CH3

4

0.1U_0402_16V4Z

CH4

CH1

1

CM1293-04SO_SOT23-6

Change P/N as SC300000B00


VGA ONLY 2 1

3 4

2 1

3 4

2 1

3 4

2 1

3 4

B

VGA_TXCLK+ VGA_TXCLK0_0404_4P2R_5% VGA_TXOUT2+ VGA_TXOUT20_0404_4P2R_5% VGA_TXOUT1+ VGA_TXOUT10_0404_4P2R_5% VGA_TXOUT0+ VGA_TXOUT00_0404_4P2R_5%

DISO@RP2 DISO@ RP2 TXOUT2+ TXOUT2DISO@RP4 DISO@ RP4 TXOUT1+ TXOUT1DISO@RP6 DISO@ RP6 TXOUT0+ TXOUT0DISO@RP8 DISO@ RP8 I2CC_SCL I2CC_SDA

0_0402_5% 2 DISO@ 1 R270 0_0402_5% 2 1 R272 DISO@

VGA_LCD_CLK VGA_LCD_DAT

VGA_TXCLK+ <18> VGA_TXCLK- <18> VGA_TXOUT2+ <18> VGA_TXOUT2- <18>

<5> APU_BLPWM

VGA_TXOUT1+ <18> VGA_TXOUT1- <18>

<31> EC_INVT_PWM <18> VGA_INVT_PWM

VGA_TXOUT0+ <18> VGA_TXOUT0- <18>

INVT_PWM

1 2 R1098 UMA@ 0_0402_5% 1 2 R158 DISO@ 0_0402_5% 1 2 R1099 @ 0_0402_5%

1

TXCLK+ TXCLK-

R1100 100K_0402_5% 2

B

VGA_LCD_CLK <19> VGA_LCD_DAT <19>

UMA ONLY TXCLK+ TXCLK-

1 2

4 3

1 2

4 3

1 2

4 3

1 2

4 3

UMA@RP1 UMA@ RP1 TXOUT2+ TXOUT2UMA@RP3 UMA@ RP3 TXOUT1+ TXOUT1UMA@RP5 UMA@ RP5 TXOUT0+ TXOUT0UMA@RP7 UMA@ RP7

A

I2CC_SCL I2CC_SDA

APU_TXCLK+ APU_TXCLK0_0404_4P2R_5% APU_TXOUT2+ APU_TXOUT20_0404_4P2R_5% APU_TXOUT1+ APU_TXOUT10_0404_4P2R_5% APU_TXOUT0+ APU_TXOUT00_0404_4P2R_5%

0_0402_5% 2 UMA@ 1 R269 0_0402_5% 2 1 R271 UMA@

APU_LCD_CLK APU_LCD_DATA

APU_TXCLK+ <5> APU_TXCLK- <5> APU_TXOUT2+ <5> APU_TXOUT2- <5> APU_TXOUT1+ <5> APU_TXOUT1- <5> APU_TXOUT0+ <5> APU_TXOUT0- <5> A

APU_LCD_CLK <5> APU_LCD_DATA <5>

Compal Secret Data

Security Classification 2010/08/20

Issued Date

2011/08/20

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc. LVDS/CAMERA Document Number

Rev 1.0

LA-7092P P5WE6/H6/S6 Wednesday, November 24, 2010

Sheet 1

10

of

47

5

4

3

2

@ R521 0_0603_5% 1 2

+3VS

1

W=40mils

HDMI connector

2

+HDMI_5V_OUT 1

1

2

C690 0.1U_0402_16V4Z

1

HDMI_SCLK HDMI_R_D0+ HDMI_R_D1-

S

D

HDMI_R_D1+ HDMI_R_D2-

HDMI_SDATA

HDMI_R_D2+

Q128 BSH111 1N_SOT23-3 @

1 0_0402_5%

@ 2 R816

1 0_0402_5%

2 R172

HDMI_SDATA HDMI_SCLK

HDMI_R_CK+ HDMI_R_D0-

Q86 BSH111 1N_SOT23-3

3

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

+HDMI_5V_OUT

HDMI_R_CK-

2

1

JHDMI1 HDMI_HPD

2

1.1A_6V_SMD1812P110TF

Change P/N SCS00002000

R161 2K_0402_5%

1

2

2

1 +HDMI_5V

D

G

R973 2 DISO@ 1 0_0402_5%

<19> VGA_HDMI_SDATA

R522

1

S

R972 2

<5> APU_HDMI_DATA

2

F2

CH491DPT_SOT23-3 2K_0402_5%

0_0402_5% 1

2

3

UMA@ 1 0_0402_5%

+5VS

R965

2

R971 2 DISO@ 1 0_0402_5%

<19> VGA_HDMI_SCLK

1

UMA@ 1 0_0402_5%

D7

+HDMI_5V_OUT

G

R970 2

<5> APU_HDMI_CLK

1

D

R968

4.7K_0402_5%

R966

4.7K_0402_5%

2

+3VS

SM070001310 400ma 90ohm@100mhz DCR 0.3 R514 1

1 L68 WCM-2012-900T_0805 @ 4 C

1

HDMI_C_TX0-

R516 1

2

2 1 1 1 1 1 1 1 1 1 1

UMA@2 UMA@2 UMA@2 UMA@2 UMA@2 UMA@2 UMA@2 UMA@2

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

HDMI_C_TX2-_R HDMI_C_TX2+_R HDMI_C_TX1-_R HDMI_C_TX1+_R HDMI_C_TX0-_R HDMI_C_TX0+_R HDMI_C_CLK-_R HDMI_C_CLK+_R

2 DISO@ 1 R977 0_0402_5%

<5> APU_HDMI_HPD

2 UMA@ 1 R981 0_0402_5%

2 150K_0402_5%

HDMI_C_TX1-

R518 1

2

E Q34 MMBT3904_NL_SOT23-3

0_0402_5%

HDMI_R_D0-

C

2 3 0_0402_5%

HDMI_R_D0+

2

0_0402_5%

HDMI_R_D1-

4

3

2 3

R517 1

2

0_0402_5%

HDMI_R_D1+

HDMI_C_TX2-

R520 1

2

0_0402_5%

HDMI_R_D2-

1 L70 WCM-2012-900T_0805 @ 4

R528 365K_0402_1% @

1

HDMI_C_TX1+

HDMI_HPD

1

R984 R985 R986 R987 R988 R989 R990 R991

<19> VGA_HDMI_DET

3 2

HDMI_R_CK+

HDMI_C_TX2+

1

2

4

3

R519 1

2

2 3 HDMI_R_D2+

0_0402_5%

B

2

APU_HDMI_TX2N APU_HDMI_TX2P APU_HDMI_TX1N APU_HDMI_TX1P APU_HDMI_TX0N APU_HDMI_TX0P APU_HDMI_CLKN APU_HDMI_CLKP

HDMI_C_TX2-_R HDMI_C_TX2+_R HDMI_C_TX1-_R HDMI_C_TX1+_R HDMI_C_TX0-_R HDMI_C_TX0+_R HDMI_C_CLK-_R HDMI_C_CLK+_R

3

From APU

<5> <5> <5> <5> <5> <5> <5> <5>

0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5%

1

From VGA

DISO@2 DISO@2 DISO@2 DISO@2 DISO@2 DISO@2 DISO@2 DISO@2

4

3 0_0402_5%

R530 10K_0402_5% 2

B

1 1 1 1 1 1 1 1

1 R525

2

R515 1

C

2 B

1

HDMI_C_TX0+

1 L54 WCM-2012-900T_0805 @ 4 R527 0_0402_5%

Use common via on related pair

3

2

2

0_0402_5% @

+3VS

4 2

L69 WCM-2012-900T_0805 @ 4 R524

2

R513 1

HDMI_R_CK-

0_0402_5%

2

1

HDMI_C_CLK+

1

R974 R975 R976 R978 R979 R980 R982 R983

D

HDMI_C_CLK-

VGA_HDMI_TXD2VGA_HDMI_TXD2+ VGA_HDMI_TXD1VGA_HDMI_TXD1+ VGA_HDMI_TXD0VGA_HDMI_TXD0+ VGA_HDMI_TXCVGA_HDMI_TXC+

20 21 22 23

SUYIN_100042MR019S153ZL CONN@

Place closed to JHDMI1

<19> <19> <19> <19> <19> <19> <19> <19>

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

1 0.1U_0402_16V7K HDMI_C_TX2- R509 1 1 0.1U_0402_16V7K HDMI_C_TX2+ R508 1

2 2

499_0402_1% 499_0402_1%

HDMI_C_TX1-_R HDMI_C_TX1+_R

C510 C511

2 2


2 2

499_0402_1% 499_0402_1%


C512 C513

2 2


2 2

499_0402_1% 499_0402_1%

HDMI_C_CLK-_R HDMI_C_CLK+_R

C514 C515

2 2

1 0.1U_0402_16V7K HDMI_C_CLK- R501 1 1 0.1U_0402_16V7K HDMI_C_CLK+ R500 1

2 2

499_0402_1% 499_0402_1%

2 G

+HDMI_5V_OUT R512

A

1

2 2

D

3

C508 C509

S

2N7002_SOT23 Q87

2010/08/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

100K_0402_5%

2011/08/20

Deciphered Date

Title

2

A


1

Place closed to JHDMI1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI Connector Rev 1.0

LA-7092P P5WE6/H6/S6

Date:

5

4

3

2

Sheet

Wednesday, November 24, 2010 1

11

of

47

A

B

C

D

E

W=40mils D14

1

D33 PJDLC05C_SOT23-3 @

CRT_R

L57 1

2 FCM2012CF-800T06_2P

CRT_B

L59 1

2 FCM2012CF-800T06_2P

CRT_B_1

2

2

C694

1

2

10P_0402_50V8J

2

10P_0402_50V8J

C693

2

10P_0402_50V8J

C692

150_0402_1%

R533

150_0402_1%

R532

R531

150_0402_1%

1

CRT_G_1

1

2 FCM2012CF-800T06_2P

1

L58 1

1

C697

1

C695

2 10P_0402_50V8J

1

2

CH491DPT_SOT23-3 1.1A_6VDC_FUSE 1

Change P/N SCS00002000

C691 0.1U_0402_16V4Z

1

2

CRT_R_1

CRT_G

1

1

W=40mils

1


+CRT_VCC

F1

2

1

2

+R_CRT_VCC

2

3

3

CRT Connector

2

+5VS

1

C696

JCRT1

6 11 1 7 12 2 8 13 3 9 14 4 10 15 5

T95PAD

1

2

2 10P_0402_50V8J 10P_0402_50V8J

1

2

T97PAD

C698

G G

C-H_13-12201513 CONN@

100P_0402_50V8J

+CRT_VCC C699 1

2 0.1U_0402_16V4Z

R537 2

L60 1 2 FCM2012CF-800T06_2P

1 10K_0402_5%

16 17

P/N : DC060003V00 F/P : SUYIN_070546HR015M21MZR_15P-T

CRT_HSYNC_2 DSUB_12

2

A

Y

CRT_HSYNC_1

4

C700 10P_0402_50V8J

G

CRT_HSYNC

L81 1 2 FCM2012CF-800T06_2P

U23

OE#

P

1

2

5

2

1

CRT_VSYNC_2 1

2

2

1

C702 10P_0402_50V8J

C703 2 68P_0402_50V8J

3

74AHCT1G125GW _SOT353-5

DSUB_15

1 C704 68P_0402_50V8J

+CRT_VCC

2

P 2

A

U19

Y

4

CRT_VSYNC_1

3

G

CRT_VSYNC

1

5

2 0.1U_0402_16V4Z

OE#

C701 1

74AHCT1G125GW _SOT353-5

Close to Conn side +CRT_VCC 3

3

<5> APU_CRT_DDC_SCL

<19> VGA_CRT_R <19> VGA_CRT_G 4

From VGA

<19> VGA_CRT_B <19> VGA_CRT_HSYNC <19> VGA_CRT_VSYNC <19> VGA_CRT_DATA <19> VGA_CRT_CLK

R998 2 UMA@ 1 0_0402_5% CRT_HSYNC

APU_CRT_VSYNC

R999 2 UMA@ 1 0_0402_5% CRT_VSYNC

APU_CRT_DDC_SDA

R1000 2 UMA@ 1 0_0402_5%

CRT_DATA

APU_CRT_DDC_SCL

R1001 2 UMA@ 1 0_0402_5%

CRT_CLK

DSUB_12

VGA_CRT_R

R1002 2 DISO@ 1 0_0402_5%

CRT_R

VGA_CRT_G

R1003 2 DISO@ 1 0_0402_5%

CRT_G

VGA_CRT_B

R1004 2 DISO@ 1 0_0402_5%

CRT_B

VGA_CRT_HSYNC

R1005 2 DISO@ 1 0_0402_5% CRT_HSYNC

VGA_CRT_VSYNC

R1006 2 DISO@ 1 0_0402_5% CRT_VSYNC

VGA_CRT_DATA

R1007 2 DISO@ 1 0_0402_5%

CRT_DATA

VGA_CRT_CLK

R1008 2 DISO@ 1 0_0402_5%

CRT_CLK

1

DSUB_15

B

1

3

CRT_CLK

Q129 BSH111 1N_SOT23-3 @ 2 R1009

1 0_0402_5%

@ 2 R1010

1 0_0402_5% 4

Compal Secret Data


Issued Date

Deciphered Date

2011/08/20

C

Title

Compal Electronics, Inc. CRT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A

CRT_DATA

3

Q89 BSH111 1N_SOT23-3

2 G

CRT_B

APU_CRT_HSYNC

2 G

CRT_G

R997 2 UMA@ 1 0_0402_5%

S

<5> APU_CRT_VSYNC <5> APU_CRT_DDC_SDA

R996 2 UMA@ 1 0_0402_5%

APU_CRT_B

R548 4.7K_0402_5%

D

<5> APU_CRT_HSYNC

APU_CRT_G

R549 4.7K_0402_5%

S

From APU

CRT_R

D

<5> APU_CRT_B

R995 2 UMA@ 1 0_0402_5%

2

<5> APU_CRT_G

APU_CRT_R

2

<5> APU_CRT_R

1

Use common via on related pair

1

+3VS

D

Size Document Number Custom

Rev 1.0


Date:

W ednesday, November 24, 2010

Sheet E

12

of

47

A

B

C

D

E

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

For DVT 1011

U31E

APU_CLKP_R APU_CLKN_R

V21 T21

<18> CLK_PCIE_VGA <18> CLK_PCIE_VGA#

R569 1 R570 1

2 0_0402_5% 2 0_0402_5%

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

V23 T23

<26> CLK_PCIE_LAN <26> CLK_PCIE_LAN#

R571 1 R572 1

2 0_0402_5% 2 0_0402_5%

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

L29 L28

R573 1 R574 1

2 0_0402_5% 2 0_0402_5%

CLK_PCIE_MINI1_R CLK_PCIE_MINI1#_R

T26 T27 <5> APU_CLKP <5> APU_CLKN

LAN

<29> CLK_PCIE_MINI1 <29> CLK_PCIE_MINI1#

WLAN

N29 N28 M29 M28

3

L24 L23

RTC_32KHI

2

22P_0402_50V8J

GPP_CLK5P GPP_CLK5N GPP_CLK6P GPP_CLK6N

N26 N27

GPP_CLK7P GPP_CLK7N

25M_CLK_X1

L26

25M_CLK_X2

L27

4

R563 20M_0603_5% 2

1

C65

1

OSC

NC

OSC

NC

P

5 G

3

1 2

<17> <17> <17> <17> <17>

2

PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27

APU_PWRGD

3

1

H_PWRGD_L <44>

FDV301N_NL_SOT23-3 Q90

+3VALW

@ U33 2 B

VGA_PWRGD

<24,43> VGA_PWRGD

1

@ C1199 1 2 0.1U_0402_16V4Z @ 1 R830

4

Y A

2

GPP_CLK8P GPP_CLK8N

ALLOW_LDTSTP/DMA_ACTIVE_L PROCHOT_L LDT_PG LDT_STP_L LDT_RST_L

PE_GPIO0 <18> PE_GPIO1 <24,35> 1 R99

@ 1 2 R838 100K_0402_5% 1 R839

2 0_0402_5%

For DVT 1011

2 10K_0402_5% VGA_PWRGD_R

RTC BATT Conn. R853 1 R575 1

2 0_0402_5% 2 22_0402_5%

LPC_CLK0 <17> LPC_CLK0_EC <31>

CONN@ JBATT2

SERIRQ <31>

SUYIN_060003HA002G202ZL

P/N: SP07000OU00 F/P: SUYIN_060003HA002G202ZL_2P

ALLOW_STOP# <5> FCH_PROCHOT# <5> APU_PWRGD <5>

+RTCBATT

APU_RST# <5>

25M_X1

25M_X2

32K_X1

C1

RTC_32KHI

32K_X2

C2

RTC_32KHO

RTCCLK INTRUDER_ALERT_L VDDBT_RTC_G

R179 1K_0402_5% +RTCVCC

D2 B2 B1

2 1 R864

C1272 1

2

W=20mils

1 C1271

2

2 510_0402_5%

1

R865

C1270

1

@

for Clear CMOS

0_0603_5%

2

Compal Secret Data


Issued Date

D23

RTC_CLK <17,31>

Deciphered Date

2011/08/20

Title

3

+CHGRTC

DAN202UT106_SC70-3 4

Compal Electronics, Inc. FCH PCIE/PCI/AI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev 1.0


Date:

A

B

3

LPC_CLK1 <17> LPC_AD0 <31> LPC_AD1 <31> LPC_AD2 <31> LPC_AD3 <31> LPC_FRAME# <31>

14M_25M_48M_OSC

3

22P_0402_50V8J

VGA_PWRGD_R

2 0_0402_5%

NC7SZ08P5X_NL_SC70-5

G21 H21 K19 G22 J24

FCH : SA000046H70 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 605P)

RTC_32KHO

2

+3VS

R164 10K_0402_5%

H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19

FCH : SA000046H60 (S IC 218-0792001 A12 HUDSON-M1 FCBGA 605P)

2

PLT_RST# <18,26,29> 2 PCIE_RST# 0_0402_5%

+RTCBATT

21807-A11-HUDSON-M1_FCBGA605

32.768KHZ_12.5PF_Q13MC14610050_10PPM

@ 2

+1.8VS

AJ6 AG6 AG4 AJ4

FCH : SA000046HA0 R1

Y4

1

1

GPP_CLK4P GPP_CLK4N

LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME_L LDRQ0_L LDRQ1_L/CLK_REQ6_L/GPIO49 SERIRQ/GPIO48

1

Close to FCH C64

GPP_CLK3P GPP_CLK3N

2

Y3

1M_0603_5% R576

25MHZ_20PF_7A25000012

4

GPP_CLK2P GPP_CLK2N

INTE_L/GPIO32 INTF_L/GPIO33 INTG_L/GPIO34 INTH_L/GPIO35

RTC

C67 27P_0402_50V8J 1 2

GPP_CLK1P GPP_CLK1N

P29 P28

L25

<29> CLK_SD_48M

2

C66 27P_0402_50V8J

GPP_CLK0P GPP_CLK0N

U

1

SLT_GFX_CLKP SLT_GFX_CLKN

P25 M25

T29 T28

Follow result by vender 10/11

U_HT_CLKP U_HT_CLKN

LPC

T25 V25

NB_HT_CLKP NB_HT_CLKN

C1233 150P_0402_50V8J

Y 4 1 A @ 1 R174 R582 8.2K_0402_5% U28 NC7SZ08P5X_NL_SC70-5

1

2 0_0402_5% 2 0_0402_5%

1

+

R162 1 R163 1

NB_DISP_CLKP NB_DISP_CLKN

2 33_0402_5%

-

U29 U28

<5> APU_DISP_CLKP <5> APU_DISP_CLKN

PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN

CLOCK GENERATOR

APU_DISP_CLKP_R APU_DISP_CLKN_R

R175 1

2

M23 P23

2 0_0402_5% 2 0_0402_5%

0.1U_0402_16V4Z

1

close to FCH within 1" R564 1 R565 1

A_RST#

B

2

PCIE_FRX_DTX_P2 PCIE_FRX_DTX_N2 PCIE_FRX_DTX_P3 PCIE_FRX_DTX_N3

GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N

2

D

AA22 Y21 AA25 AA24 W23 V24 W24 W25

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N

1

C1234 1 2

5

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

PCIE_FTX_DRX_P2 PCIE_FTX_DRX_N2 PCIE_FTX_DRX_P3 PCIE_FTX_DRX_N3

PCIE_CALRP PCIE_CALRN

+3VALW

PAD T92 AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5 AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11 AD7

P

2 2 2 2

AA28 AA29 Y29 Y28 Y26 Y27 W28 W29

V2

S

2

1 1 1 1

AD29 AD28

PCI I/F

<26> <26> <29> <29>

C61 C62 C717 C63

PCIE_FTX_C_DRX_P2 PCIE_FTX_C_DRX_N2 PCIE_FTX_C_DRX_P3 PCIE_FTX_C_DRX_N3

590_0402_1% 2K_0402_1%

<17> <17> <17> <17>

G

LAN WLAN

1 1

AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31 CBE0_L CBE1_L CBE2_L CBE3_L FRAME_L DEVSEL_L IRDY_L TRDY_L PAR STOP_L PERR_L SERR_L REQ0_L REQ1_L/GPIO40 REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42 GNT0_L GNT1_L/GPO44 GNT2_L/GPO45 GNT3_L/CLK_REQ7_L/GPIO46 CLKRUN_L LOCK_L

PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4

G

<26> <26> <29> <29>

2 2

UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

PCIRST_L

PAD T96

W2 W1 W3 W4 Y1

3

R560 R561

+PCIE_VDDAN

UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N

PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38 PCICLK4/14M_OSC/GPO39

0.1U_0402_16V4Z

AE24 AE23 AD25 AD24 AC24 AC25 AB25 AB24

PCIE_RST_L A_RST_L

2

AD26 AD27 AC28 AC29 AB29 AB28 AB26 AB27

1

UMI_RX0P_C UMI_RX0N_C UMI_RX1P_C UMI_RX1N_C UMI_RX2P_C UMI_RX2N_C UMI_RX3P_C UMI_RX3N_C

2

UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N

0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

1

<6> <6> <6> <6> <6> <6> <6> <6>

2 2 2 2 2 2 2 2

1U_0402_6.3V4Z

UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N

1 1 1 1 1 1 1 1

0.1U_0402_16V4Z

1

<6> <6> <6> <6> <6> <6> <6> <6>

C53 C54 C55 C56 C57 C58 C59 C60

PCI CLKS

P1 L1

PCI EXPRESS I/F

PCIE_RST# A_RST#

<31> A_RST#

C

D

Wednesday, November 24, 2010

Sheet E

13

of

47

A

B

C

D

E

+3VALW

@

USB_OC7# 2 10K_0402_5% EC_LID_OUT# 2 10K_0402_5% USB_OC5# 2 10K_0402_5% ODD_DA#_FCH 2 10K_0402_5% ODD_DETECT# 2 10K_0402_5%

U31A

<31> SLP_S3# <31> SLP_S5# <31> PBTN_OUT#

1

+3VS

<31> EC_GA20 <31> EC_KBRST# <31> EC_SCI# <31> EC_SMI#

LAN_CLKREQ# 2 10K_0402_5% MINI1_CLKREQ# 2 10K_0402_5% NB_PWRGD 2 4.7K_0402_5% FCH_SMCLK0 2 2.2K_0402_5% FCH_SMDAT0 2 2.2K_0402_5%

@

1 R817 1 R818 1 R597 1 R598 1 R599

R580 2

@

+3VALW

R579 1

@

2 10K_0402_5% <26,29> FCH_PCIE_WAKE# <5> H_THERMTRIP#

R581 2

1 0_0402_5% <26> LAN_CLKREQ#

5 P 4

@

@

@ @

G

VGATE <31,44> <29> MINI1_CLKREQ#

NC7SZ08P5X_NL_SC70-5 U30 @

1

VRAM_SEL 2 2.2K_0402_5% 2 100K_0402_5%

VRAM_Freq : 1->900Hz 0-> 800Hz*

USB_OC7# <31> EC_LID_OUT#

USB_OC5# ODD_DA#_FCH ODD_DETECT# USB_OC2# USB_OC1#

<30> ODD_DA#_FCH <30> ODD_DETECT# <33> USB_OC2# <33> USB_OC1# <33> USB_OC0#

VGA_CLKREQ#_R 2 10K_0402_5% FCH_SMCLK1 2 10K_0402_5% FCH_SMDAT1 2 10K_0402_5% EC_RSMRST# 2 2.2K_0402_5% HDA_BITCLK 2 10K_0402_5% HDA_SDIN0 2 10K_0402_5% HDA_SDOUT 2 10K_0402_5%

R583 1 R165 1

<27> HDA_BITCLK_AUDIO <27> HDA_SDOUT_AUDIO <27> HDA_SDIN0

+3VALW

R593

2 10K_0402_5% 2 10K_0402_5% 2 10K_0402_5%

R596

1

2 10K_0402_5%

R600

1

1

1

1

+3VALW +3VALW +3VALW

2

2

2

PX@ VGA@ R912 R911 R910 10K_0402_5% 10K_0402_5% 10K_0402_5%

GPIO189 GPIO190 GPIO191

T85 T86

2

2

2

2 10K_0402_5%

1

1

1

+3VALW BACO@ WOPX@ WOVGA@ R915 R914 R913 10K_0402_5% 10K_0402_5% 10K_0402_5%

PAD PAD

T1 T4 L6 L5 T9 U1 U3 T2 U2 T5 V5 P5 M5 P9 T7 P7 M7 P4 M9 V7

GPIO187 E23 GPIO188 E24 F21 G29 GPIO189 GPIO190 GPIO191

D27 F28 F29 E27

AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 AZ_SDIN3/GPIO170 AZ_SYNC AZ_RST_L GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST_L GBE_PHY_INTR

GBE LAN

1

M3 N1 L2 M2 M1 M4 N2 P2

USB_FSD0P/GPIO185 USB_FSD0N

H9 J8

USB_HSD13P USB_HSD13N

B12 A12


F11 E11


E14 E12

PS2_DAT/SDA4/GPIO187 PS2_CLK/SCL4/GPIO188 SPI_CS2_L/GBE_STAT2/GPIO166 FC_RST_L/GPO160

USB_RCOMP 1

2 11.8K_0402_1%

1

USB_HSD[13:0]P/N: USB P/N pairs with trace lengths up to 10" and have a decoupling 5.6-pF capacitor footprint placed near the USB connector or device.

Root

J12 J14 A13 B13 D13 C13

USB20_P8 <29> USB20_N8 <29>

MINI1-WLAN

G12 G14

USB20_P7 <33> USB20_N7 <33>

BT

Root

G16 G18

USB20_P6 <29> USB20_N6 <29>

CardReader

EHCI CTL DEV 19, Fn 2

USB_HSD5P USB_HSD5N

D16 C16

USB20_P5 <10> USB20_N5 <10>

Camera

USB_HSD4P USB_HSD4N

B14 A14

USB_HSD3P USB_HSD3N

E18 E16

USB_HSD2P USB_HSD2N

J16 J18

USB20_P2 <33> USB20_N2 <33>

USB/B (Right)

Root

USB_HSD1P USB_HSD1N

B17 A17

USB20_P1 <33> USB20_N1 <33>

USB/B (Right)

EHCI CTL DEV 18, Fn 2

A16 B16

USB20_P0 <33> USB20_N0 <33>

USB Conn (Left)

USB_HSD8P USB_HSD8N

BLINK/USB_OC7_L/GEVENT18_L USB_OC6_L/IR_TX1/GEVENT6_L USB_OC5_L/IR_TX0/GEVENT17_L USB_OC4_L/IR_RX0/GEVENT16_L USB_OC3_L/AC_PRES/TDO/GEVENT15_L USB_OC2_L/TCK/GEVENT14_L USB_OC1_L/TDI/GEVENT13_L USB_OC0_L/TRST_L/GEVENT12_L

R578 G19

J10 H11

USB_HSD9P USB_HSD9N

USB_HSD7P USB_HSD7N USB_HSD6P USB_HSD6N

USB_HSD0P USB_HSD0N

SCL2/GPIO193 SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196 EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

EMBEDDED CTRL

R5911 R5921

3

HDA_BITCLK HDA_SDOUT HDA_SDIN0

2 33_0402_5% HDA_SYNC 2 33_0402_5% HDA_RST#

R589 1 R590 1

<27> HDA_SYNC_AUDIO <27> HDA_RST_AUDIO#

Pull-down for enable high performance mode 20100527 (required for M1)

2 33_0402_5% 2 33_0402_5%

H3 D1 E4 D4 E8 F7 E7 F8

A10

USB_FSD1P/GPIO186 USB_FSD1N


CLK_REQ4_L/SATA_IS0_L/GPIO64 CLK_REQ3_L/SATA_IS1_L/GPIO63 SMARTVOLT1/SATA_IS2_L/GPIO50 CLK_REQ0_L/SATA_IS3_L/GPIO60 SATA_IS4_L/FANOUT3/GPIO55 SATA_IS5_L/FANIN3/GPIO59 SPKR_GPIO66 SCL0_GPIO43 SDA0_GPIO47 SCL1_GPIO227 SDA1_GPIO228 CLK_REQ2_L/FANIN4_GPIO62 CLK_REQ1_L/FANOUT4_GPIO61 IR_LED_L/LLB_L/GPIO184 SMARTVOLT2/SHUTDOWN_L/GPIO51 DDR3_RST_L/GEVENT7_L GBE_LED0/GPIO183 GBE_LED1/GEVENT9_L GBE_LED2/GEVENT10_L GBE_STAT0/GEVENT11_L CLK_REQG_L/GPIO65_OSCIN

HD AUDIO

1 R173 1 R587 1 R588 1 R606 1 R607 1 R608 1 R609

@

A

RSMRST_L

USB OC

1 R626 1 R404

+3VS

2

EC_PWROK <31>

1

3

@ C112 0.1U_0402_16V7K

2

2

B

Y

USB_RCOMP

USB 2.0

<27> FCH_SPKR <8,9,29> FCH_SMCLK0 <8,9,29> FCH_SMDAT0

AD19 AA16 AB21 AC18 AF20 AE19 AF19 AD22 AE22 FCH_SMCLK1 F5 FCH_SMDAT1 F4 AH21 AB18 E1 AJ21 H4 VRAM_SEL D5 D7 G5 K3 VGA_CLKREQ#_R AA20

USBCLK/14M_25M_48M_OSC

10mils and <1"

GPIO

+3VS @ C111 0.1U_0402_16V7K 1 2

<44> FCH_PWRGD

G1

<31> EC_RSMRST#

1 0_0402_5%

PCI_PME_L/GEVENT4_L RI_L/GEVENT22_L SPI_CS3_L/GBE_STAT1/GEVENT21_L SLP_S3_L SLP_S5_L PWR_BTN_L PWR_GOOD SUS_STAT_L TEST0 TEST1/TMS TEST2 GA20IN/GEVENT0_L KBRST_L/GEVENT1_L LPC_PME_L/GEVENT3_L LPC_SMI_L/GEVENT23_L GEVENT5_L SYS_RESET_L/GEVENT19_L WAKE_L/GEVENT8_L IR_RX1/GEVENT20_L THRMTRIP_L/SMBALERT_L/GEVENT2_L NB_PWRGD

USB 1.1

J2 K1 D3 F1 H1 F2 FCH_PWRGD H5 G6 B3 T82PAD C4 T83PAD F6 T84PAD AD21 AE21 K2 J29 H2 J1 H6 F3 J6 NB_PWRGD AC19

<31> EC_SWI#

USB MISC

1 R929 1 R930 1 R931 1 R932 1 R933

AI/WAKE UP EVENTS

USB_OC2# 2 10K_0402_5% USB_OC1# 2 10K_0402_5% USB_OC0# 2 10K_0402_5% FCH_SIC 2 10K_0402_5% FCH_SID 2 10K_0402_5% FCH_PCIE_WAKE# 2 10K_0402_5%

1 R870 1 R871 1 R872 1 R603 1 R604 1 R605

KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208 KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

D25 F23 B26 E26 F25 E22 F22 E21

2

GPIO193 GPIO194

R584 2 R586 2

< Wakeup>

1 10K_0402_5% 1 10K_0402_5% FCH_SIC <5> FCH_SID <5>

EC_PWM2 EC_PWM3

EC_PWM2 <17> EC_PWM3 <17>

G24 G25 E28 E29 D29 D28 C29 C28

3

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

PS2KB_DAT/GPIO189 PS2KB_CLK/GPIO190 PS2M_DAT/GPIO191 PS2M_CLK/GPIO192 21807-A11-HUDSON-M1_FCBGA605

4

SKU_ID (GPIO189)

SKU_ID : 1->VGA* 0->UMA

PX_FN (GPIO190)

PX_Function : 1->PX Enable* 0->PX Disable

PX_SEL (GPIO191)

PX_SEL : 1->PX 3.0* 0->PX 4.0

4

GPIO

189

190

191

UMA DISO PX3.0 PX4.0

0 1 1 1

0 0 1 1

1 1 1 0

2010/08/20

Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title


FCH HDA/USB/AI Rev 1.0


Date:

A

B

C

D


Sheet E

14

of

47

A

B

C

D

E

1

1

U31B

HDD

C656 C658

<30> SATA_ITX_DRX_P0 <30> SATA_ITX_DRX_N0

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

1 1

SATA_ITX_C_DRX_P0 AH9 SATA_ITX_C_DRX_N0 AJ9

<30> SATA_DTX_C_IRX_N0 <30> SATA_DTX_C_IRX_P0

ODD

SATA_TX0P SATA_TX0N

AJ8 AH8 C648 C649


2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

1 1

SATA_RX0N SATA_RX0P

SATA_ITX_C_DRX_P1 AH10 SATA_ITX_C_DRX_N1 AJ10 AG10 AF10

SATA_RX1N SATA_RX1P

AG12 AF12

SATA_TX2P SATA_TX2N

AJ12 AH12

SATA_RX2N SATA_RX2P

AH14 AJ14

SATA_TX3P SATA_TX3N

AG14 AF14

SATA_RX3N SATA_RX3P

AG17 AF17

SATA_TX4P SATA_TX4N

AJ17 AH17

SATA_RX5N SATA_RX5P

10 mils and < 1" 2 1K_0402_1% 2 931_0402_1%

1 1

SATA_CALRP SATA_CALRN

AB14 AA14

SATA_CALRP SATA_CALRN

AD11

<32> SATA_LED# R616 1 1 3

@ C107

25M_SATA_X1 AD16

22P_0402_50V8J 2

@ C106 22P_0402_50V8J 1 2

1M_0603_5% R861

@

25M_SATA_X2 AC16

SATA_X2

T78PAD

J5 E2 K4 K9 G2

SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1_L/GPIO165 ROM_RST_L/GPIO161

SPI ROM

25MHZ_20PF_7A25000012 FCH_SI_SPI_SO FCH_SO_SPI_SI FCH_SPICLK FCH_SPICS#/FSEL#

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180 VIN6/GBE_STAT3/GPIO181 VIN7/GBE_LED3/GPIO182

SATA_X1

@ Y7

FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54

TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT_L/GPIO174 TEMP_COMM

SATA_ACT_L/GPIO67

2 10K_0402_5% 2 1

+3VS

HW MONITOR

SATA_TX5P SATA_TX5N

AH19 AJ19 R610 R611

FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136 FC_ADQ9/GPIOD137 FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

SATA_RX4N SATA_RX4P

AJ18 AH18

+AVDD_SATA

SERIAL ATA

2

FC_OE_L/GPIOD145 FC_AVD_L/GPIOD146 FC_WE_L/GPIOD148 FC_CE1_L/GPIOD149 FC_CE2_L/GPIOD150 FC_INT1/GPIOD144 FC_INT2/GPIOD147

SATA_TX1P SATA_TX1N

GPIOD


FC_CLK FC_FBCLKOUT FC_FBCLKIN

NC1 NC2

AH28 AG28 AF26 AF28 AG29 AG26 AF27 AE29 AF29 AH27 AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

2

W5 W6 Y9

ODD_PWR

ODD_PWR <30>

W7 V9 W8 B6 A6 A5 B5 C7

TEMPIN0 R612 2 TEMPIN1 R613 2 TEMPIN2 R614 2 R615 2

1 1 1 1

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

A3 B4 A4 C5 A7 B7 B8 A8

GPIO175 GPIO176 GPIO177 GPIO178 GPIO179 GPIO180 GPIO181 GPIO182

1 1 1 1 1 1 1 1

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

R617 R618 R619 R620 R621 R622 R623 R624

2 2 2 2 2 2 2 2

@

3

VIN6/GBE_STAT3/GPIO181 Enable integrated pull-down/up and leave unconnected

G27 Y2


@ +3VS

@ 1 R504

2 0_0603_5%

C784 1

2 0.1U_0402_16V4Z

FCH_+SPI_VCC U32

4

+3VS

R507 1 R491 1

@ @

FCH_SPICS#/FSEL# FCH_SPI_WP# 2 4.7K_0402_5% FCH_SPI_HOLD# 2 4.7K_0402_5%

1 3 7 4

CS# WP# HOLD# GND

VCC SCLK SI SO

8 6 5 2

FCH_SPICLK_R FCH_SO_SPI_SI FCH_SI_SPI_SO

R510 1

@

2 0_0402_5% FCH_SPICLK 4

MX25L1605DM2I-12G SOP 8P SA00002TO00 @

2010/08/20

Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title


FCH-SATA/SPI Rev 1.0


Date:

A

B

C

D


Sheet E

15

of

47

M6 P8

PLL

2

2

1

0.1U_0402_16V7K

C93

1

C94

1

FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

L48 2

+1.1VALW

+VDDAN_11_USB C11 D11

88.6mA

VDDCR_11_S_1 VDDCR_11_S_2

F26 G26

VDDPL_33_USB_S

VDDAN_11_USB_S_1 VDDAN_11_USB_S_2

VDDAN_33_HWM_S VDDXL_33_S

C99

1


+3VALW

2

C776

C775

C778

1

2

C68

2

10U_0603_6.3V6M

10U_0603_6.3V6M

C109

10U_0603_6.3V6M

C743

C75

1U_0402_6.3V6K

C74

1U_0402_6.3V6K

0.1U_0402_16V7K

330U_D2_2.5VY_R9M

10U_0603_6.3V6M

C71

C118

1U_0402_6.3V6K

C117

1U_0402_6.3V6K

C119

+VDDIO_AZ

58mA

1

Add VGA@ For DVT

1

2

1

2

1

2

+VDDCR_11_USB @ L107 2 1 5 FBMA-L11-160808-221LMT 0603

F19

3

C989 @

Reserve +1.1VALW

1

2

+VDDAN33_HWM +VDDXL_33_S

L20

FB

1U_0402_6.3V6K 2 1 2

1

2

1

2

L47 2 1 FBMA-L11-201209-221LMA30T_0805

+1.1VALW

+AVDD_USB

11.4mA

D6

GND

1

2

+VDDPL11

16.1mA

VIN VOUT

APL5317

+VDDPL33

65.3mA

L22

@ U85

EN

46.5mA

M21

4

+3VALW

+VDDCR_11_USB

5mA

0.1U_0402_16V7K

2

1

0.1U_0402_16V7K

2

1

1U_0402_6.3V6K

C97

1

1U_0402_6.3V6K

C96

2

1

L49 2

1

+3VS

FBMA-L11-160808-221LMT_2P

3

+VDDIO_AZ

+3VALW @ 1 R634 1 R635

2 0_0603_5% 2 0_0603_5%

+3VS

For DVT 1011

1

2

C98 2.2U_0603_6.3V6K

For 3V AZ device

+VDDAN33_HWM

L53 2 1 FBMA-L11-160808-221LMT_2P

2 2.2U_0603_6.3V6K C100

4

1

2 +VDDPL33

C782

L52 2 1 FBMA-L11-160808-221LMT_2P

1

10U_0603_6.3V6M

2

+VDDPL11 +1.1VALW

1

+1.1VS

2

1

0.1U_0402_16V7K

2 2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C777 1

L50 2 1 FBMA-L11-201209-221LMA30T_0805 C108

2 1 FBMA-L11-160808-221LMT_2P

C73

15.3mA

A11 B11

2

10U_0603_6.3V6M

+3VS

+1.1VS

C70

C738

165.2mA

M8


1

2

+AVDD_SATA +VDDPL_33_SATA

0.1U_0402_16V7K

0.1U_0402_16V7K

49.5mA

3

L51

1

FBMA-L11-201209-221LMA30T_0805

1

+3VALW

A21 D21 B21 K10 L10 J9 T6 T8

VDDPL_33_SYS

L43 2

+ 2


VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

VDDPL_11_SYS_S

2

C92

VDDIO_GBE_S_1 VDDIO_GBE_S_2

VDDIO_AZ_S

2

1

1

M10

L7 L9

VDDCR_11_USB_S_1 VDDCR_11_USB_S_2

2

1

10U_0603_6.3V6M

2

VDDAN_33_USB_S_1 VDDAN_33_USB_S_2 VDDAN_33_USB_S_3 VDDAN_33_USB_S_4 VDDAN_33_USB_S_5 VDDAN_33_USB_S_6 VDDAN_33_USB_S_7 VDDAN_33_USB_S_8 VDDAN_33_USB_S_9 VDDAN_33_USB_S_10 VDDAN_33_USB_S_11 VDDAN_33_USB_S_12

+1.1VS

VGA@

C91

C89

C88

2

1

0.1U_0402_16V7K

2

1

1U_0402_6.3V6K

C87

1

1U_0402_6.3V6K

2

10U_0603_6.3V6M

C86

10U_0603_6.3V6M

C85

2

1

A18 A19 A20 B18 B19 B20 C18 C20 D18 D19 D20 E19

USB I/O

1

534.5mA

+1.1VS

0.1U_0402_16V7K

+AVDD_USB

1

2

1

0.1U_0402_16V7K

CORE S5

2

1

C90

VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7

L46 FBMA-L11-201209-221LMA30T_0805

2

C82

AJ20 AF18 AH20 AG19 AE18 AD18 AE16

VDDPL_33_SATA

1

2

V1

VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2

3.3V_S5 I/O

+AVDD_SATA

1345.2mA

+3VALW

2

1

15.5mA +VDDPL_33_SATA AD14

2

2.2U_0603_6.3V6K

VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8

SERIAL ATA

Change 0603 size For DVT 2

U26 V22 V26 V27 V28 V29 W22 W26

1

C84

+PCIE_VDDAN

2

1

1U_0402_6.3V6K

1115.6mA

VDDIO_33_GBE_S VDDPL_33_PCIE

1

E

382.9mA

+VDDAN_11_CLK

K28 K29 J28 K26 J21 J20 K21 J22

2

C81

C80

1

AE28

2

1

2.2U_0603_6.3V6K

22.5mA +VDDPL33_PCIE

1

C83

C76 C79

1

2

VDDRF_GBE_S

979.4mA

1U_0402_6.3V6K

2

2

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

N13 R15 N17 U13 U17 V12 V18 W12 W18

2.2U_0603_6.3V6K

2

1

0.1U_0402_16V7K

2

1

1U_0402_6.3V6K

C105

1

C78

2 1 FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

L45

C77

+1.1VS

10U_0603_6.3V6M

2

VDDIO_18_FC_1 VDDIO_18_FC_2 VDDIO_18_FC_3 VDDIO_18_FC_4

GBE LAN

1

AF22 AE25 AF24 AC22

PCI EXPRESS

L44 2 1 FBMA-L11-160808-221LMT_2P

+3VS

1

0.1U_0402_16V7K

C69

C746

@

0.16mA

2.2U_0603_6.3V6K

1

2

0.1U_0402_16V7K

For DVT 1011

@

0.1U_0402_16V7K

1

4.7U_0603_6.3V6K

C744

R633 2

@

2

FLASH I/O

1

+VDDIO_18_FC

2

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

C72

R632 @ 2 0_0603_5%

VDDIO_33_PCIGP_1 VDDIO_33_PCIGP_2 VDDIO_33_PCIGP_3 VDDIO_33_PCIGP_4 VDDIO_33_PCIGP_5 VDDIO_33_PCIGP_6 VDDIO_33_PCIGP_7 VDDIO_33_PCIGP_8 VDDIO_33_PCIGP_9 VDDIO_33_PCIGP_10 VDDIO_33_PCIGP_11 VDDIO_33_PCIGP_12

D

C95

1

AH1 V6 Y19 AE5 AC21 AA2 AB4 AC8 AA7 AA9 AF7 AA19

0.1U_0402_16V7K

C116

0.1U_0402_16V7K

C115

C114

C113

0.1U_0402_16V7K

1

2

CLKGEN I/O

1

1

2

GPIO I/F implemented: tied to +1.8V_S0 GPIO I/F not implemented: tied to +1.8V_S0 or 0 ohm to ground

1

+1.8VS

10U_0603_6.3V6M

1

2

POWER

U31C

42mA

0_0402_5%

1

2

CORE S0

2

C

PCI/GPIO I/O

C121

Change 0603 size For DVT 10U_0603_6.3V6M

+3VS

B

0.1U_0402_16V7K

A

4

L55 +3VS

2 1 FBMA-L11-160808-221LMT_2P C120 1

2010/08/20

Issued Date


Compal Secret Data


2 2.2U_0603_6.3V6K

2011/08/20

Deciphered Date

Title


FCH PWR Rev 1.0


Date:

A

B

C

D

Tuesday, November 16, 2010

Sheet E

16

of

47

4

3

U31D

VSSXL

P21 P20 M22 M24 M26 P22 P24 P26 T20 T22 T24 V20 J23

VSSIO_PCIECLK_1 VSSIO_PCIECLK_2 VSSIO_PCIECLK_3 VSSIO_PCIECLK_4 VSSIO_PCIECLK_5 VSSIO_PCIECLK_6 VSSIO_PCIECLK_7 VSSIO_PCIECLK_8 VSSIO_PCIECLK_9 VSSIO_PCIECLK_10 VSSIO_PCIECLK_11 VSSIO_PCIECLK_12 VSSIO_PCIECLK_13

PCI_CLK3

PCI_CLK4

LPC_CLK0 LPC_CLK1

WATCHDOG TIMER ENABLE

ALLOW PCIE GEN2

USE DEBUG STRAP

NON Fusion CLOCK Mode

internal EC ENABLE

VSSPL_SYS

RTC_CLK

Internal CLKGEN Mode

EC_PWM2 EC_PWM3 LPC ROM (H.L)

S5 PLUS MODE DISABLED

DEFAULT

D

DEFAULT

DEFAULT DEFAULT

WATCHDOG TIMER DISABLE

PULL LOW

FORCE PCIE GEN1

IGNORE DEBUG STRAP

Fusion CLOCK Mode

internal EC DISABLE

DEFAULT

DEFAULT

DEFAULT

External CLKGEN Mode

S5 PLUS MODE ENABLED

SPI ROM(L,H)

DEFAULT

+3VALW

1

+3VALW

1

+3VALW

1

+3VALW

1

+3VALW

1

+3VS

1

+3VS

1

1

+3VS

1

+3VS

2

2

2

2

2

2

2

C

1

1

1

1

1

1

1

PCI_CLK2 PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 EC_PWM3 RTC_CLK

1

<13> <13> <13> <13> <13> <13> <14> <14> <13,31>

2

2

R649 R636 R637 R638 R639 R166 R594 R550 R551 @ @ @ @ @ @ 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

2

2

R640 R641 R642 R643 R167 R601 R602 R625 @ @ @ @ 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2

R650

2

VSSAN_HWM

PCI_CLK1

2

D8 M19

Check Internal PU/PD

2

EFUSE

PULL HIGH

1

PCI_CLK2

2

Y4

REQUIRED STRAPS

AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8

1

VSSIO_USB_1 VSSIO_USB_2 VSSIO_USB_3 VSSIO_USB_4 VSSIO_USB_5 VSSIO_USB_6 VSSIO_USB_7 VSSIO_USB_8 VSSIO_USB_9 VSSIO_USB_10 VSSIO_USB_11 VSSIO_USB_12 VSSIO_USB_13 VSSIO_USB_14 VSSIO_USB_15 VSSIO_USB_16 VSSIO_USB_17 VSSIO_USB_18 VSSIO_USB_19 VSSIO_USB_20 VSSIO_USB_21 VSSIO_USB_22 VSSIO_USB_23 VSSIO_USB_24 VSSIO_USB_25 VSSIO_USB_26 VSSIO_USB_27 VSSIO_USB_28

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52

GND

C

A9 B10 K11 B9 D10 D12 D14 D17 E9 F9 F12 F14 F16 C9 G11 F18 D9 H12 H14 H16 H18 J11 J19 K12 K14 K16 K18 H19

VSSIO_SATA_1 VSSIO_SATA_2 VSSIO_SATA_3 VSSIO_SATA_4 VSSIO_SATA_5 VSSIO_SATA_6 VSSIO_SATA_7 VSSIO_SATA_8 VSSIO_SATA_9 VSSIO_SATA_10 VSSIO_SATA_11 VSSIO_SATA_12 VSSIO_SATA_13 VSSIO_SATA_14 VSSIO_SATA_15 VSSIO_SATA_16 VSSIO_SATA_17 VSSIO_SATA_18 VSSIO_SATA_19

2

D

Y14 Y16 AB16 AC14 AE12 AE14 AF9 AF11 AF13 AF16 AG8 AH7 AH11 AH13 AH16 AJ7 AJ11 AJ13 AJ16

2

2

5

M20

B

B

H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20

DEBUG STRAPS FCH M1 HAS 15K INTERNAL PU FOR PCI_AD[27:23]

DEFAULT

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23


BY PCI PLL

ILA AUTORUN Enabled

Check AD29,AD28 strap function

A

Getting Value from I2C EPROM

R644 R645 R646 R647 R648 @ @ @ @ @ 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

Reserved

check default

A


Compal Secret Data

Security Classification Issued Date

FC PLL byed

2

PULL LOW

2010/08/20

Deciphered Date

2011/08/20

Title


Date:

5

4

3

1

DEFAULT

DEFAULT

<13> <13> <13> <13> <13>

2

DEFAULT

Required Setting

1

Disable I2C ROM

2

ILA AUTORUN Selects Disabled FC PLL

1

DEFAULT

PCI_AD23 Enable ROM Straps

PCI_AD24

2

USE internal PLL generated PLL CLK

PCI_AD25

1

PULL HIGH

PCI_AD26

2

PCI_AD27

1

VSSIO_PCIECLK_14 VSSIO_PCIECLK_15 VSSIO_PCIECLK_16 VSSIO_PCIECLK_17 VSSIO_PCIECLK_18 VSSIO_PCIECLK_19 VSSIO_PCIECLK_20 VSSIO_PCIECLK_21 VSSIO_PCIECLK_22 VSSIO_PCIECLK_23 VSSIO_PCIECLK_24 VSSIO_PCIECLK_25 VSSIO_PCIECLK_26 VSSIO_PCIECLK_27

2

FCH-VSS/Strap Document Number

Rev 1.0


Sheet 1

17

of

47

5

4

3

2

1

GFX PCIE LANE REVERSAL

add for VB . U2G

D

<6> PCIE_FTX_C_GRX_P[0..3] <6> PCIE_FTX_C_GRX_N[0..3]

PCIE_FTX_C_GRX_P[0..3]

PCIE_GTX_C_FRX_P[0..3]

PCIE_FTX_C_GRX_N[0..3]

PCIE_GTX_C_FRX_N[0..3]

PCIE_FTX_C_GRX_P0 PCIE_FTX_C_GRX_N0

AA38 Y37


Y35 W36


W38 V37


V35 U36

PCIE_RX0P PCIE_RX0N

PCIE_TX0P PCIE_TX0N

Y33 Y32

PCIE_GTX_FRX_P0 C1 PCIE_GTX_FRX_N0 C2

1

PCIE_GTX_C_FRX_P[0..3] <6>

W33 W32


1

2 1 VGA@

PCIE_RX2P PCIE_RX2N

PCIE_TX2P PCIE_TX2N

U33 U32


1

2 1 VGA@

PCIE_RX3P PCIE_RX3N

PCIE_TX3P PCIE_TX3N

U30 U29


1

U38 T37

PCIE_RX4P PCIE_RX4N

PCIE_TX4P PCIE_TX4N

T33 T32

T35 R36

PCIE_RX5P PCIE_RX5N

PCIE_TX5P PCIE_TX5N

T30 T29

2 VGA@ 2 VGA@

2 1 VGA@

2

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

0.1U_0402_16V7K PCIE_GTX_C_FRX_P1 0.1U_0402_16V7K PCIE_GTX_C_FRX_N1

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N


TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N


P35 N36

PCIE_RX7P PCIE_RX7N

N38 M37

PCIE_RX8P PCIE_RX8N

M35 L36

PCIE_RX9P PCIE_RX9N

L38 K37 K35 J36 J38 H37 H35 G36 B

PCIE_RX6P PCIE_RX6N

G38 F37 F35 E37

PCIE_RX10P PCIE_RX10N PCIE_RX11P PCIE_RX11N PCIE_RX12P PCIE_RX12N

PCI EXPRESS INTERFACE

R38 P37

PCIE_TX6P PCIE_TX6N

P30 P29

PCIE_TX8P PCIE_TX8N

N33 N32

PCIE_TX9P PCIE_TX9N

N30 N29

PCIE_TX10P PCIE_TX10N PCIE_TX11P PCIE_TX11N PCIE_TX12P PCIE_TX12N

PCIE_RX13P PCIE_RX13N

PCIE_TX13P PCIE_TX13N





VGA_INVT_PWM <10> VGA_ENVDD <10>

R2 1 2 10K_0402_5% VGA@ AK35 AL36 AJ38 AK37 AH35 AJ36 AG38 AH37 AF35 AG36

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

AP34 AR34

VGA_TXCLK+ VGA_TXCLK-

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

AW37 AU35

VGA_TXOUT0+ VGA_TXOUT0-


AR37 AU39



AP35 AR35


LVTMDP

P33 P32

PCIE_TX7P PCIE_TX7N

AK27 AJ27

TXOUT_U3P TXOUT_U3N

VGA@

C

VARY_BL DIGON


2 VGA@

PCIE_TX1P PCIE_TX1N

PCIE_RX1P PCIE_RX1N

LVDS CONTROL

PCIE_GTX_C_FRX_N[0..3] <6>

2 1 VGA@

D

R1 10K_0402_5% 1 2 VGA@

U2A

TXOUT_L3P TXOUT_L3N

VGA_TXCLK+ <10> VGA_TXCLK- <10> VGA_TXOUT0+ <10> VGA_TXOUT0- <10>

C

VGA_TXOUT1+ <10> VGA_TXOUT1- <10> VGA_TXOUT2+ <10> VGA_TXOUT2- <10>

AN36 AP37

2160809000A11SEYMOU_FCBGA962

L33 L32

Seymour@

L30 L29 K33 K32 J33 J32 B

K30 K29 H33 H32 +3VSG

CLOCK PCIE_REFCLKP PCIE_REFCLKN

1

5

<13> PE_GPIO0

2

<13,26,29> PLT_RST#

1

B

U16 PX@ Y

A

4 VGA_RST#

PERSTB 3

AA30

PCIE_CALRN

Y30 1 VGA@ 2 R3 1.27K_0402_1% Y29 1 VGA@ 2 +1.0VSG R6 2K_0402_1%

P

PCIE_CALRP

2 VGA@ 1 AH16 R5 10K_0402_5% PWRGOOD VGA_RST#

R394 2.2K_0402_5% @

CALIBRATION

G

AB35 AA36

2

<13> CLK_PCIE_VGA <13> CLK_PCIE_VGA#

AH16 Accessiable for "Test Purposes" Connect to GND for "Normal Operation"



1 DISO@ 2 R159 0_0402_5%

Seymour@

Seymour XT P/N: SA000047H10 (S IC 216-0809000 A11 SEYMOUR XT M2) Robson XT P/N: SA00004DR20 (S IC 216-0774211 A11 Robson XT M2 ) A

A

U2 Robson@

Robson A11 (SA00004DR20)

Issued Date


Compal Secret Data


Robson XT-M2 A11

2010/08/20

2011/08/20

Deciphered Date

Title

Vancouver_ PCIE / LVDS


Rev 1.0


Date:

5

4

3

2


Sheet 1

18

of

47

5

4

3

2

1

U2B

Setting

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable 0: Tx de-emphasis diabled for mobile mode 1: Tx de-emphasis enabled (Defailt setting for desktop)

GPIO1

D

CONFIG[2] CONFIG[1] CONFIG[0]

GPIO13,12,11 (config 2,1,0) : a) If BIOS_ROM_EN = 1, then Config[2:0] defines the ROM type.

GPIO13 GPIO12 GPIO11

BIOS_ROM_EN

b) If BIOS_ROM_EN = 0, then Config[2:0] defines the primary memory aperture size.

GPIO22

AUD[1] AUD(0)

RESERVED

memory apertures CONFIG[3:0] 128 MB 000 256 MB 001 * 64 MB 010

NC on Park and Robson VRAM_ID0 VRAM_ID1 VRAM_ID2 VRAM_ID3

001

Enable external BIOS ROM device 0: Diable, 1: Enable

GPIO2

NC on Park, Robson and Seymour

1

0

00: No audio function; 10: Audio for DisplayPort only; 01: Audio for DisplayPort and HDMI if adapter is detected; 11: Audio for both DisplayPort and HDMI 0= s the PCI-E device as 2.5 GT/s capable at power-on 1= s the PCI-E device as 5.0 GT/s capable at power-on 5.0 GT/s capability will be controlled by software

HSYNC VSYNC

BIF_GEN2_EN

1

11

0

H2SYNC Internal use only. THIS PAD HAS AN INTERNAL (GENLK_CLK) PULL-DOWN AND MUST BE 0 V AT RESET. The pad may be left unconnected GPIO8 GPIO21 GENERICC GPIO5


DNI

+3VSG

C

AJ21 AK21

+3VSG VGA@ R11 VGA@ R13 @ R15 @ R16 @ R17 VGA@ R18 @ R19 @ R20 DISO@R21 DISO@ R21 DISO@R22 DISO@ R22 @ R23 @ R24 @ R25 @ R26 @ R27 @ R28

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

VGA_GPIO0 VGA_GPIO1 VGA_GPIO2 SOUT_GPIO8 SIN_GPIO9 VGA_GPIO11 VGA_GPIO12 VGA_GPIO13 VGA_CRT_VSYNC VGA_CRT_HSYNC GENERICC V2SYNC H2SYNC BB_EN_GPIO21 ROMSE_GPIO22 VGA_GPIO5

10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

R12 R14

1 VGA@ 1 VGA@

1

1

1

0

0

1

0

GPU_VID1 BB_EN_GPIO21 ROMSE_GPIO22

<43> GPU_VID1 T2 T3 T4 T5 T6 T7

<4 pcs>

1

GENERICC

<4 pcs>

SOUT_GPIO8

2 1

2 1

2 1

2

2

1

1

1

1 2 1 2

2

470ohm/1A

S

TYPE 1

HOLD

2 VGA@

W VCC

1

2 VGA@

GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16 GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 NC_GENERICF_HPD5 NC_GENERICG_HPD6

27MCLK R53

27MCLK XTALOUT

+DPLL_VDDC 1

2 VGA@

1 R49 1 R50

B BB

DAC1

HSYNC VSYNC RSET

70mA 45mA

AVDD AVSSQ VDD1DI VSS1DI R2/NC R2B/NC G2/NC G2B/NC B2/NC B2B/NC

C/NC Y/NC COMP/NC

@ @

AV33 AU34

H2SYNC/GENLK_CLK V2SYNC/GENLK_VSYNC

AK32 AL31

C36 VGA@ 18P_0402_50V8J

2 VGA@

1

2 VGA@

C34 0.1U_0402_16V4Z

2 VGA@

27MHZ_16PF_X5H027000FG1H

1

C33 1U_0402_6.3V4Z

VGA@ 1

10mil

+TSVDD

C32 10U_0603_6.3V6M

L5 BLM18AG121SN1D_0603 2 1 VGA@ 1

AJ32 AJ33

THERM#

GND

VGA_SMB_DA2

6

2

5

R7 0_0402_5%

4

VGA_SMB_DA2

D

2 4.7K_0402_5%

+3VSG

3

EC_SMB_CK2

EC_SMB_CK2

<5,31>

EC_SMB_DA2

<5,31>

Q1B VGA@ DMN66D0LDW-7_SOT363-6

1

AT21 AR20

Q1A

EC_SMB_DA2 6 VGA@ DMN66D0LDW-7_SOT363-6


AU22 AV21 AT23 AR22

<12>

VGA_CRT_G

<12>

AF37 AE38

VGA_CRT_B

<12>

AC36 AC38

VGA_CRT_HSYNC VGA_CRT_VSYNC

AB34

R30

AD34 AE34

+AVDD

AC33 AC34

+VDD1DI

1 VGA@

10mil

1

AD30 AD31

1

1

AF30 AF31

1

AC32 AD32 AF32

2 VGA@

AD29 AC29

H2SYNC V2SYNC

2mAA2VDDQ/NC

AD33

+A2VDDQ

XTALIN XTALOUT

10mil

1

1

2 VGA@

10mil

AA29

R48 715_0402_1% 1 2 VGA@

DDC1CLK DDC1DATA

DDC2CLK DDC2DATA AUX2P AUX2N

NC_DDCCLK_AUX4P NC_DDCDATA_AUX4N DDCCLK_AUX5P DDCDATA_AUX5N

TS_FDO DDC6CLK DDC6DATA

TS_A/NC

NC_DDCCLK_AUX7P NC_DDCDATA_AUX7N


AM26 AN26

VGA_HDMI_SCLK VGA_HDMI_SDATA

1

1

2

L78 BLM18AG121SN1D_0603 1 +1.8VSG VGA@

120ohm/0.3A

+3VSG

VGA_CRT_CLK VGA_CRT_DATA

VGA@ R33 VGA@ R34

1 1

2 10K_0402_5% 2 10K_0402_5%

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA@ R35 VGA@ R36 VGA@ R37

1 1 1

2 150_0402_1% 2 150_0402_1% 2 150_0402_1%


2 VGA@ L79 BLM18AG121SN1D_0603 2 1 +1.8VSG VGA@

120ohm/0.3A

NC on Whistler and Seymour

2 VGA@

2 VGA@

1

VGA@ 1

VGA@ 1

2

2

2

VGA_HDMI_SCLK <11> VGA_HDMI_SDATA <11>

+3VSG

In Whistler and Seymour, change to GENLK_CLK, GENLK_VSYNC for Global Swap Lock on multiple GPUs

+1.8VSG

Except A2VSSQ change to TSVSSQ, others are NC on Whistler and Seymour

HDMI

AM27 AL27 AM19 AL19 AN20 AM20 AL30 AM30


AL29 AM29 AN21 AM21

VGA_CRT_CLK VGA_CRT_DATA

VGA_CRT_CLK <12> VGA_CRT_DATA <12>

CRT

A

AJ30 AJ31 AK30 AK29

Issued Date

3

B

2 VGA@

VGA@ 1



Compal Secret Data


Seymour@

2 VGA@

2 VGA@

2 VGA@

AF33

XO_IN XO_IN2

1

10mil

+A2VDD

AUX1P AUX1N

20mA

<12> <12>

499_0402_1%

2 VGA@

AC30 AC31

75mA

THERMAL

2

C

10mil

AG33

PLL/CLOCK DPLL_VDDC

DPLUS DMINUS

VGA_CRT_R

AE36 AD35

130mAA2VDD/NC

R2SET/NC DPLL_PVDD DPLL_PVSS

AD39 AD37

2010/08/20

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4

1 R8 VGA@

Title

Vancouver_Strape/DP/HDMI//CRT Size Document Number Custom

2

Rev 1.0


Date: 5

THM_ALERT#

1

VGA@

R10 4.7K_0402_5% VGA@

AU20 AT19

+VDD1DI

VREFG

TSVDD TSVSS

VGA_SMB_CK2

AT17 AR16

AG31 AG32

100mAVDD2DI/NC

DDCCLK_AUX3P DDCDATA_AUX3N AF29 AG29

AU16 AV15

DAC2

DDC/AUX AN31

2 AW34 0_0402_5% 2 AW35 0_0402_5%

GPU_THERM_D+ GPU_THERM_D-

120ohm/0.3A

C35 VGA@ 18P_0402_50V8J

HPD1

G GB

125mA

AL31 Manhattan/Vancouver is NC, Boardway is ADC input(0-1V) use measure regulator current or temperature

VGA@

2

10mil

+1.8VSG

XTALOUT

Y1

2 VGA@

4

VSS

M25P10-AVMN6P C31 @ 0.1U_0402_16V4Z

1M_0603_5%

1

2 VGA@

ALERT#

C23 10U_0603_6.3V6M

2

Q

C

+1.0VSG L4 BLM18AG121SN1D_0603 2 1 VGA@

2 VGA@

1

R9 4.7K_0402_5% VGA@

C20 10U_0603_6.3V6M

470ohm/1A

1

AM32 AN32

D-

7

Not share via for other GND R RB

10mil +DPLL_PVDD

4

SDATA

VGA_SMB_CK2

8

SCLK

D+

+3VSG

AT15 AR14

C24 0.1U_0402_16V4Z

1

NC_TX4P_DPD1P NC_TX4M_DPD1N

A2VSSQ/TSVSSQ

+1.8VSG

L3 BLM18AG121SN1D_0603 2 1 VGA@ 1

AH13

3

VDD

+3VSG

AU14 AV13

C19 0.1U_0402_16V4Z

@ A

8

AK24

2

Address 1001 101X b

AT33 AU32

C22 1U_0402_6.3V4Z

3

@ 2 1 R52 0_0402_5% 2

+VGA_VREF

C27 1U_0402_6.3V4Z

7 R51 0_0402_5% @ 2 1

DPD


15mil

2 VGA@ 0.1U_0402_16V4Z

1

C30 1U_0402_6.3V4Z

+3VSG

1

2 249_0402_1%

C29 0.1U_0402_16V4Z

ROMSE_GPIO22

2 499_0402_1%

1 VGA@ C21

@

D

1 VGA@

R43

PD-Reset

C28 10U_0603_6.3V6M

6

R42

C26 0.1U_0402_16V4Z

@

+1.8VSG

Internal PD

C25 10U_0603_6.3V6M

5


VSS2DI/NC VRAM_ID0 VRAM_ID1 VRAM_ID2 VRAM_ID3

U5 CLK_GPIO10

NC_TXCDP_DPD3P NC_TXCDM_DPD3N

@

FLASH ROM SIN_GPIO9

VGA_HDMI_DET

<11> VGA_HDMI_DET

R47 10K_0402_5%

R46 10K_0402_5%

R45 10K_0402_5%

R44 10K_0402_5%

@

R41 10K_0402_5%

R40 10K_0402_5%

R39 10K_0402_5%

R38 10K_0402_5% @

@

TX2P_DPC0P TX2M_DPC0N

U4 VGA@ 1

1032ARMZ-2REEL_MSOP8

AR32 AT31

C18 1U_0402_6.3V4Z

NC on Park

+1.8VSG

@


SCL SDA

B

@

DPC

AV31 AU30

C17 10U_0603_6.3V6M

Hynix SA000041S40 Vega-die H5TQ1G63DFR-11C

1


AR30 AT29

C52 10U_0603_6.3V6M

T1

<4 pcs>

TXC_DPC3P TXCCM_DPC3N

2

GPU_THERM_D+ 2200P_0402_50V7K VGA@ 1 2 C11 GPU_THERM_D-

C14 10U_0603_6.3V6M

1

0

<size>

TX5P_DPB0P TX5M_DPB0N

VGA_HDMI_TXD2+ <11> VGA_HDMI_TXD2- <11>

C16 0.1U_0402_16V4Z

0

Hynix SA000032420 Orion-die H5TQ1G63BFR-12C


AT27 AR26

1 C10 VGA@

HDMI

C13 0.1U_0402_16V4Z

GPU_VID0 THM_ALERT#

64MX16

DPB


C15 1U_0402_6.3V4Z

VGA_ENBKL SOUT_GPIO8 SIN_GPIO9 CLK_GPIO10 VGA_GPIO11 VGA_GPIO12 VGA_GPIO13

Location VRAM_ID3 VRAM_ID2 VRAM_ID1 VRAM_ID0



AU26 AV25

C12 1U_0402_6.3V4Z

AH20 AH18 AN16 AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AM23 AN23 AK23 AL24 AM24 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

VGA_GPIO5 <10> VGA_ENBKL 1 R29 VGA@ 10K_0402_5%

Samsung SA00004GS10 G-die K4W1G1646G-BC11

TXCBP_DPB3P TXCBM_DPB3N

I2C AK26 AJ26

VGA_GPIO0 VGA_GPIO1 VGA_GPIO2

change VGA@ as DISO@ For PVT

<43> GPU_VID0

SWAPLOCKA SWAPLOCKB

TX2P_DPA0P TX2M_DPA0N

GENERAL PURPOSE I/O

GPIO_0 will use to control PSI in the future product

2

VRAM

NC_DVPCNTL_MVP_0 NC_DVPCNTL_MVP_1 NC_DVPCNTL_0 NC_DVPCNTL_1 NC_DVPCNTL_2 NC_DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 NC_DVPDATA_17 NC_DVPDATA_18 NC_DVPDATA_19 NC_DVPDATA_20 NC_DVPDATA_21 NC_DVPDATA_22 NC_DVPDATA_23

2 4.7K_0402_5% 2 4.7K_0402_5%

VGA_LCD_CLK VGA_LCD_DAT

<10> VGA_LCD_CLK <10> VGA_LCD_DAT

Robson (XT)/Seymour(XT)

TX1P_DPA1P TX1M_DPA1N AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12

AT25 AR24

+3VSG

5

Transmitter Power Saving Enable 0: 50% Tx output swing for mobile mode 1: full Tx output swing (Default setting for Desktop)

GPIO0

DPA

VGA_HDMI_TXC+ <11> VGA_HDMI_TXC- <11>

2

TX_PWRS_ENB

TX0P_DPA2P TX0M_DPA2N

MUTI GFX

0

AU24 AV23

2

VGA Disable determines 0: VGA Controller capacity enabled 1: The device will not be recognized as the system’s VGA controller

GPIO9

TXCAP_DPA3P TXCAM_DPA3N

0.1U_0402_16V4Z

VGA_DIS

External VGA Thermal Sensor Don't have this strap on Whistler and Seymour

0

2

VIP Device Strap Enable indicates to the software driver V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset VIP_DEVICE_EN (GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device

1

Pin Straps description

1

Strap Name


Sheet

19

of

47

5

4

3

2

1

Robson,Seymour only single channel memory (channel B only) D

D U2D

DDR2 GDDR3/GDDR5 DDR3

K23 K19

NC_CASA0B NC_CASA1B

K20 K17

NC_CSA0B_0 NC_CSA0B_1

K24 K27

NC_CSA1B_0 NC_CSA1B_1

M13 K16

NC_CKEA0 NC_CKEA1

K21 J20

1

NC_RASA0B NC_RASA1B

2

NC_MVREFDA NC_MVREFSA

J14 H14

1

L18 L20

NC_CLKA1 NC_CLKA1B

VGA@

2

+1.5VSG

R60 VGA@ 40.2_0402_1% MVREFSB

R61 VGA@ 100_0402_1%

1

C40 VGA@

NC_WEA0B NC_WEA1B

K26 L15

R66 R67 R69

2 VGA@ 2 VGA@ 2 VGA@

1 243_0402_1% M12 1 243_0402_1% M27 1 243_0402_1% AH12

MEM_CALRP1 NC_MEM_CALRP0 NC_MEM_CALRP2

NC_MAA0_8 NC_MAA1_8

H23 J19

TESTEN 2 VGA@ 1 R65 5.11K_0402_1% TEST_MCLK TEST_YCLK C41 VGA@ 0.1U_0402_16V4Z

GDDR5

NC_MEM_CALRN0 MEM_CALRN1 NC_MEM_CALRN2

2

2

1

1


MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1

WCKB0_0/DQMB_0 WCKB0B_0/DQMB_1 WCKB0_1/DQMB_2 WCKB0B_1/DQMB_3 WCKB1_0/DQMB_4 WCKB1B_0/DQMB_5 WCKB1_1/DQMB_6 WCKB1B_1/DQMB_7 GDDR5/DDR2/GDDR3 EDCB0_0/QSB_0/RDQSB_0 EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2 EDCB0_3/QSB_3/RDQSB_3 EDCB1_0/QSB_4/RDQSB_4 EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6 EDCB1_3/QSB_7/RDQSB_7

H3 H1 T3 T5 AE4 AF5 AK6 AK5

DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7

F6 K3 P3 V5 AB5 AH1 AJ9 AM5

QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7

DDBIB0_0/QSB_0B/WDQSB_0 DDBIB0_1/QSB_1B/WDQSB_1 DDBIB0_2/QSB_2B/WDQSB_2 DDBIB0_3/QSB_3B/WDQSB_3 DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5 DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7

G7 K1 P1 W4 AC4 AH3 AJ8 AM3

QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7

T7 W7

ODTB0 ODTB1

ADBIB0/ODTB0 ADBIB1/ODTB1

AD28

TESTEN

AK10 AL10

CLKTESTA CLKTESTB

DQMB#[0..7]

QSB[0..7]

L9 L8

CLKB0 CLKB0#

CLKB1 CLKB1B

AD8 AD7

CLKB1 CLKB1#

RASB0B RASB1B

T10 Y10

RASB0# RASB1#

CASB0B CASB1B

W10 AA10

CASB0# CASB1#

CSB0B_0 CSB0B_1

P10 L10

CSB0#_0

CSB1B_0 CSB1B_1

AD10 AC10

CSB1#_0

CKEB0 CKEB1

U10 AA11

CKEB0 CKEB1

WEB0B WEB1B

N10 AB11

WEB0# WEB1#

MAB0_8 MAB1_8

T8 W8

DRAM_RST


DQMB#[0..7]

<23>

<23>

C

<23>

ODTB0 <23> ODTB1 <23> CLKB0 <23> CLKB0# <23> CLKB1 <23> CLKB1# <23> RASB0# <23> RASB1# <23> CASB0# <23> CASB1# <23>

B

CSB0#_0 <23> CSB1#_0 <23> CKEB0 <23> CKEB1 <23> WEB0# <23> WEB1# <23>

VGA@ 1

<23>

QSB#[0..7]

MAB13 <23> R68

AH11

<23>

B_BA[0..2]

QSB[0..7]

QSB#[0..7]

CLKB0 CLKB0B

MVREFDB MVREFSB

MAB[0..12]

B_BA[0..2]

VGA@ 2

1

10_0402_5% 1

2

C43 120P_0402_50V8

1 243_0402_1% L27 1 243_0402_1% N12 1 243_0402_1% AG12

P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

R71 VGA@ 5.11K_0402_1%

2 VGA@ 2 VGA@ 2 VGA@

MVREFDB Y12 MVREFSB AA12

C42 VGA@ 0.1U_0402_16V4Z

R62 R63 R64

2

MAB[0..12]

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8 MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12 MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

1

MVREFDA MVREFSA

+1.5VSG

H27 G27

1

C38

0.1U_0402_16V4Z

B

NC_CLKA0 NC_CLKA0B

MVREFDB

DQB0_0/DQB_0 DQB0_1/DQB_1 DQB0_2/DQB_2 DQB0_3/DQB_3 DQB0_4/DQB_4 DQB0_5/DQB_5 DQB0_6/DQB_6 DQB0_7/DQB_7 DQB0_8/DQB_8 DQB0_9/DQB_9 DQB0_10/DQB_10 DQB0_11/DQB_11 DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14 DQB0_15/DQB_15 DQB0_16/DQB_16 DQB0_17/DQB_17 DQB0_18/DQB_18 DQB0_19/DQB_19 DQB0_20/DQB_20 DQB0_21/DQB_21 DQB0_22/DQB_22 DQB0_23/DQB_23 DQB0_24/DQB_24 DQB0_25/DQB_25 DQB0_26/DQB_26 DQB0_27/DQB_27 DQB0_28/DQB_28 DQB0_29/DQB_29 DQB0_30/DQB_30 DQB0_31/DQB_31 DQB1_0/DQB_32 DQB1_1/DQB_33 DQB1_2/DQB_34 DQB1_3/DQB_35 DQB1_4/DQB_36 DQB1_5/DQB_37 DQB1_6/DQB_38 DQB1_7/DQB_39 DQB1_8/DQB_40 DQB1_9/DQB_41 DQB1_10/DQB_42 DQB1_11/DQB_43 DQB1_12/DQB_44 DQB1_13/DQB_45 DQB1_14/DQB_46 DQB1_15/DQB_47 DQB1_16/DQB_48 DQB1_17/DQB_49 DQB1_18/DQB_50 DQB1_19/DQB_51 DQB1_20/DQB_52 DQB1_21/DQB_53 DQB1_22/DQB_54 DQB1_23/DQB_55 DQB1_24/DQB_56 DQB1_25/DQB_57 DQB1_26/DQB_58 DQB1_27/DQB_59 DQB1_28/DQB_60 DQB1_29/DQB_61 DQB1_30/DQB_62 DQB1_31/DQB_63

2

VGA@

J21 G19

R57 VGA@ 100_0402_1%

C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5

GDDR5

2

2

C39 0.1U_0402_16V4Z

R59 VGA@ 100_0402_1%

1

NC_ADBIA0/ODTA0 NC_ADBIA1/ODTA1

R56 VGA@ 40.2_0402_1%

1

1

MVREFSA

1

2

R58 VGA@ 40.2_0402_1%

NC_DDBIA0_0/QSA_0B/WDQSA_0 NC_DDBIA0_1/QSA_1B/WDQSA_1 NC_DDBIA0_2/QSA_2B/WDQSA_2 NC_DDBIA0_3/QSA_3B/WDQSA_3 NC_DDBIA1_0/QSA_4B/WDQSA_4 NC_DDBIA1_1/QSA_5B/WDQSA_5 NC_DDBIA1_2/QSA_6B/WDQSA_6 NC_DDBIA1_3/QSA_7B/WDQSA_7

C34 D29 D25 E20 E16 E12 J10 D7

0.1U_0402_16V4Z

+1.5VSG

A34 E30 E26 C20 C16 C12 J11 F8

+1.5VSG

2

VGA@

NC_WCKA0_0/DQMA_0 NC_WCKA0B_0/DQMA_1 NC_WCKA0_1/DQMA_2 NC_WCKA0B_1/DQMA_3 NC_WCKA1_0/DQMA_4 NC_WCKA1B_0/DQMA_5 NC_WCKA1_1/DQMA_6 NC_WCKA1B_1/DQMA_7 GDDR5/DDR2/GDDR3 NC_EDCA0_0/QSA_0/RDQSA_0 NC_EDCA0_1/QSA_1/RDQSA_1 NC_EDCA0_2/QSA_2/RDQSA_2 NC_EDCA0_3/QSA_3/RDQSA_3 NC_EDCA1_0/QSA_4/RDQSA_4 NC_EDCA1_1/QSA_5/RDQSA_5 NC_EDCA1_2/QSA_6/RDQSA_6 NC_EDCA1_3/QSA_7/RDQSA_7

A32 C32 D23 E22 C14 A14 E10 D9

1

C37

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

2

2

2

NC_MAA0_0/MAA_0 NC_MAA0_1/MAA_1 NC_MAA0_2/MAA_2 NC_MAA0_3/MAA_3 NC_MAA0_4/MAA_4 NC_MAA0_5/MAA_5 NC_MAA0_6/MAA_6 NC_MAA0_7/MAA_7 NC_MAA1_0/MAA_8 NC_MAA1_1/MAA_9 NC_MAA1_2/MAA_10 NC_MAA1_3/MAA_11 NC_MAA1_4/MAA_12 NC_MAA1_5/MAA_13_BA2 NC_MAA1_6/MAA_14_BA0 NC_MAA1_7/MAA_A15_BA1

MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63

1

1

0.1U_0402_16V4Z

R55 VGA@ 100_0402_1%

MDB[0..63]

<23> MDB[0..63]

2

MVREFDA

1

2

R54 VGA@ 40.2_0402_1% C

NC_DQA0_0/DQA_0 NC_DQA0_1/DQA_1 NC_DQA0_2/DQA_2 NC_DQA0_3/DQA_3 NC_DQA0_4/DQA_4 NC_DQA0_5/DQA_5 NC_DQA0_6/DQA_6 NC_DQA0_7/DQA_7 NC_DQA0_8/DQA_8 NC_DQA0_9/DQA_9 NC_DQA0_10/DQA_10 NC_DQA0_11/DQA_11 NC_DQA0_12/DQA_12 NC_DQA0_13/DQA_13 NC_DQA0_14/DQA_14 NC_DQA0_15/DQA_15 NC_DQA0_16/DQA_16 NC_DQA0_17/DQA_17 NC_DQA0_18/DQA_18 NC_DQA0_19/DQA_19 NC_DQA0_20/DQA_20 NC_DQA0_21/DQA_21 NC_DQA0_22/DQA_22 NC_DQA0_23/DQA_23 NC_DQA0_24/DQA_24 NC_DQA0_25/DQA_25 NC_DQA0_26/DQA_26 NC_DQA0_27/DQA_27 NC_DQA0_28/DQA_28 NC_DQA0_29/DQA_29 NC_DQA0_30/DQA_30 NC_DQA0_31/DQA_31 NC_DQA1_0/DQA_32 NC_DQA1_1/DQA_33 NC_DQA1_2/DQA_34 NC_DQA1_3/DQA_35 NC_DQA1_4/DQA_36 NC_DQA1_5/DQA_37 NC_DQA1_6/DQA_38 NC_DQA1_7/DQA_39 NC_DQA1_8/DQA_40 NC_DQA1_9/DQA_41 NC_DQA1_10/DQA_42 NC_DQA1_11/DQA_43 NC_DQA1_12/DQA_44 NC_DQA1_13/DQA_45 NC_DQA1_14/DQA_46 NC_DQA1_15/DQA_47 NC_DQA1_16/DQA_48 NC_DQA1_17/DQA_49 NC_DQA1_18/DQA_50 NC_DQA1_19/DQA_51 NC_DQA1_20/DQA_52 NC_DQA1_21/DQA_53 NC_DQA1_22/DQA_54 NC_DQA1_23/DQA_55 NC_DQA1_24/DQA_56 NC_DQA1_25/DQA_57 NC_DQA1_26/DQA_58 NC_DQA1_27/DQA_59 NC_DQA1_28/DQA_60 NC_DQA1_29/DQA_61 NC_DQA1_30/DQA_62 NC_DQA1_31/DQA_63

MEMORY INTERFACE A

1

+1.5VSG

C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5


1


MEMORY INTERFACE B

U2C


R70 2

MAB13 is for 128M*16 VRAM VRAM_RST# <23>

51.1_0402_1%

VGA@

2

R72 VGA@ 51.1_0402_1%

2

Seymour@

Seymour@

R73 VGA@ 51.1_0402_1%

A

A

Issued Date


Compal Secret Data


Deciphered Date

2011/08/20


4

3

2

Title

Vancouver_Memory Size Document Number Custom

Rev 1.0


Date:


Sheet

20

of

47

5

4

3

2

1

U2E

MEM I/O

2800mA +1.5VSG

C347 VGA@ 10U_0603_6.3V6M

C346 VGA@ 1U_0402_6.3V4Z

C345 VGA@ 1U_0402_6.3V4Z

2

2

1

2

2

C

1

+

+ C395 C394 VGA@ VGA@ 390U_2.5V_10M 330U_D2_2V_Y 2 2

L39 VGA@ 2 1 FBMA-L11-201209-121LMA50T_0805

+VDDCI

2

1

2

2

1

2

1

2

1

2

1

2

1

2

Issued Date

1

2

1

2

1

2

1

2

J7 2 @

2

4

3

1

1

2

A

Change 0603 size For DVT Compal Secret Data 2010/08/20

+VGA_CORE

2 1 FBMA-L11-201209-121LMA50T_0805

Deciphered Date

Compal Electronics, Inc. 2011/08/20


1

JUMP_43X118

L41 VGA@

C428 VGA@ 10U_0603_6.3V6M

2

2

1

C427 VGA@ 10U_0603_6.3V6M

1

1

C420 VGA@ 1U_0402_6.3V4Z

1


Seymour@

2

B

C421 VGA@ 10U_0603_6.3V6M


1

+BIF_VDDC

C426 VGA@ 1U_0402_6.3V4Z

FB_GND

2

330U ESR:10m H:5.7 P/N:SF000002O00

C425 VGA@ 1U_0402_6.3V4Z

FB_VDDCI

1

1

55mA

C424 VGA@ 1U_0402_6.3V4Z

FB_VDDC

AG28

2

2

+VGA_CORE

C383 VGA@ 1U_0402_6.3V4Z

1

1

1

C373 VGA@ 1U_0402_6.3V4Z

2

2

2

C382 VGA@ 1U_0402_6.3V4Z

1

1

1

C372 VGA@ 1U_0402_6.3V4Z

2

2

2

C381 VGA@ 1U_0402_6.3V4Z

1

1

1

C371 VGA@ 1U_0402_6.3V4Z

2

2


C423 VGA@ 1U_0402_6.3V4Z

AF28

VGA@ 390U_2.5V_10M 2

C393 VGA@ 10U_0603_6.3V6M

1

1

C419 VGA@ 1U_0402_6.3V4Z

SPVSS

1

C380 VGA@ 1U_0402_6.3V4Z

2

2

C418 VGA@ 1U_0402_6.3V4Z

AN10

D

C686 +

C370 VGA@ 1U_0402_6.3V4Z

1

1

2

C392 VGA@ 10U_0603_6.3V6M

2

2

2

1

C379 VGA@ 1U_0402_6.3V4Z

1

1

1

C391 VGA@ 10U_0603_6.3V6M

2

2

2

C390 VGA@ 10U_0603_6.3V6M

1

1

2

1

C369 VGA@ 1U_0402_6.3V4Z

2

2

1

C378 VGA@ 1U_0402_6.3V4Z

1

2

1

C368 VGA@ 1U_0402_6.3V4Z

2

1

C377 VGA@ 1U_0402_6.3V4Z

SPV10


C357 VGA@ 10U_0603_6.3V6M

1

C356 VGA@ 1U_0402_6.3V4Z

2

C355 VGA@ 1U_0402_6.3V4Z

2

C367 VGA@ 1U_0402_6.3V4Z

SPV18

AN9

FB_GND AH29 2 0_0402_5%

1

C422 VGA@ 1U_0402_6.3V4Z

VGA@

1 R375

2

4A

AM10

VOLTAGE SENESE GCORE_SEN

C334 VGA@ 1U_0402_6.3V4Z

2

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

2

C417 VGA@ 1U_0402_6.3V4Z

2

1

VDDCI#1 VDDCI#2 VDDCI#3 VDDCI#4 VDDCI#5 VDDCI#6 VDDCI#7 VDDCI#8 VDDCI#9 VDDCI#10 VDDCI#11 VDDCI#12 VDDCI#13 VDDCI#14 ISOLATED VDDCI#15 CORE I/O VDDCI#16 VDDCI#17 VDDCI#18 VDDCI#19 VDDCI#20 VDDCI#21 VDDCI#22

1

2

FBMA-L11-201209-221LMA30T_0805 2 1 +1.8VSG L34 VGA@ 1 1 220ohm/2A

FOR XT DDR3 13 A (RMS)/14.2 A(Peak)

C416 VGA@ 1U_0402_6.3V4Z

2

1

120mA

MPV18#1 MPV18#2

1


C415 VGA@ 1U_0402_6.3V4Z

1

75mA

H7 H8

2

C344 VGA@ 1U_0402_6.3V4Z

NC_VDDRHB NC_VSSRHB

2

C389 VGA@ 10U_0603_6.3V6M

V12 U12

2

C376 VGA@ 1U_0402_6.3V4Z

NC_VDDRHA NC_VSSRHA

1

C366 VGA@ 1U_0402_6.3V4Z

M20 M21

C333 VGA@ 1U_0402_6.3V4Z

VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#6

2

C414 VGA@ 0.1U_0402_16V4Z

+SPV10

75mA

C413 VGA@ 0.1U_0402_16V4Z

2 1 L40 VGA@ BLM18AG121SN1D_0603

<43> GCORE_SEN

A

AD12 AF11 AF12 AG11

C328 VGA@ 1U_0402_6.3V4Z

+MPV_18

470ohm/1A


C354 VGA@ 1U_0402_6.3V4Z

2

C412 VGA@ 1U_0402_6.3V4Z

2

+1.0VSG

AF13 AF15 AG13 AG15

PLL

C408 VGA@ 10U_0603_6.3V6M

2

1

C411 VGA@ 0.1U_0402_16V4Z

1


1

2

1

+1.0VSG 1

C388 VGA@ 10U_0603_6.3V6M

1

C402 VGA@ 0.1U_0402_16V4Z

2

2

C407 VGA@ 0.1U_0402_16V4Z

1

1

C401 VGA@ 1U_0402_6.3V4Z

1

C400 VGA@ 10U_0603_6.3V6M

2

C406 VGA@ 1U_0402_6.3V4Z

2

C405 VGA@ 0.1U_0402_16V4Z

C404 VGA@ 1U_0402_6.3V4Z

2

1

I/O AF23 AF24 AG23 AG24

+VDDR4

+SPV_18 C410 VGA@ 1U_0402_6.3V4Z

2

C409 VGA@ 10U_0603_6.3V6M

BLM18AG121SN1D_0603 2 1 +1.8VSG L38 VGA@ 1 120ohm/0.3A

C403 VGA@ 10U_0603_6.3V6M

2

1

C399 VGA@ 0.1U_0402_16V4Z

170mA

2

1

2

1

120ohm/0.3A

+1.8VSG

2

1

VGA@

BLM18AG601SN1D_2P

B

1

C398 VGA@ 1U_0402_6.3V4Z

L36 2

+1.8VSG

C397 VGA@ 10U_0603_6.3V6M

1

2

BLM18AG121SN1D_0603 2 1 L37 VGA@ 1 470ohm/1A

60mA

+VDDR3

+3VSG

Removed bead on ref137-12

VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4

1

2A

C387 VGA@ 10U_0603_6.3V6M

AF26 AF27 AG26 AG27

1

2

C327 VGA@ 1U_0402_6.3V4Z

219mA

1

2

1

C375 VGA@ 1U_0402_6.3V4Z

2

2

1

C365 VGA@ 1U_0402_6.3V4Z

2

LEVEL TRANSLATION

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24 N27 R18 R21 R23 R26 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

POWER

2

1

C386 VGA@ 0.1U_0402_16V4Z

120ohm/0.3A

1

C385 VGA@ 1U_0402_6.3V4Z

1

C384 VGA@ 10U_0603_6.3V6M

C

+VDD_CT

2 1 L35 VGA@ BLM18AG121SN1D_0603

VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32 VDDC/BIF_VDDC#33 VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41 VDDC/BIF_VDDC#42 VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58 CORE

+PCIE_VDDR 1

C374 VGA@ 1U_0402_6.3V4Z

+1.8VSG

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

504mA

C364 VGA@ 1U_0402_6.3V4Z


PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12

AA31 AA32 AA33 AA34 V28 W29 W30 Y31 AB37

C332 VGA@ 1U_0402_6.3V4Z

2

C363 VGA@ 1U_0402_6.3V4Z

1

PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8 PCIE_VDDR/PCIE_PVDD

C343 VGA@ 0.1U_0402_16V4Z

2

VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34

C353 VGA@ 1U_0402_6.3V4Z

1

PCIE AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7

C326 VGA@ 0.1U_0402_16V4Z

2

C352VGA@ 1U_0402_6.3V4Z

2

C362 VGA@ 1U_0402_6.3V4Z

1

1

C342 VGA@ 1U_0402_6.3V4Z

2

C351VGA@ 1U_0402_6.3V4Z

2

1

C341 VGA@ 1U_0402_6.3V4Z

1

2

C337 VGA@ 1U_0402_6.3V4Z

2

2

1

C350VGA@ 1U_0402_6.3V4Z

1

1

C325 VGA@ 1U_0402_6.3V4Z

2

2

2

C361 VGA@ 1U_0402_6.3V4Z

2

1

1

1

C331VGA@ 1U_0402_6.3V4Z

1

2

2

C360 VGA@ 10U_0603_6.3V6M

2

2

1

1

C330VGA@ 1U_0402_6.3V4Z

1

1

2

C359 VGA@ 10U_0603_6.3V6M

2

2

C336 VGA@ 10U_0603_6.3V6M

1

C358 VGA@ 10U_0603_6.3V6M

2

C335 MAN@ 10U_0603_6.3V6M

1

1

2

C329VGA@ 1U_0402_6.3V4Z

2

C349VGA@ 1U_0402_6.3V4Z

1

C348VGA@ 1U_0402_6.3V4Z

390U ESR:10m H:5.7 P/N:SF000002O00

2

1

C340 VGA@ 1U_0402_6.3V4Z

2

D

1

C324 VGA@ 1U_0402_6.3V4Z

2

1

C339 VGA@ 1U_0402_6.3V4Z

+

C322 VGA@ 390U_2.5V_10M

C338 VGA@ 1U_0402_6.3V4Z

1

C323 VGA@ 1U_0402_6.3V4Z

1

2

Title

Vancouver_Power/GND Size Document Number Custom

Rev 1.0


Date:


Sheet

21

of

47

5

4

3

2

1

U2F

D

U2H

DP C/D POWER

+1.8VSG

L42 VGA@ BLM18AG121SN1D_0603 2 1

470ohm/1A

150mA

+1.0VSG

110mA

+DPCD_VDD10

+DPCD_VDD10

+1.8VSG

AN19 AP18 AP19 AW20 AW22

PX_EN <24>

1

2

C443 VGA@ 1U_0402_6.3V4Z

2 BACO@ 0_0402_5%

2

C442 VGA@ 0.1U_0402_16V4Z

2 R378

1

AW18

+DPEF_VDD18

AH34 AJ34

+DPEF_VDD10

AL33 AM33

470ohm/1A 1

1

440mA

DP/DPA_VSSR#1 DP/DPA_VSSR#2 DP/DPA_VSSR#3 DP/DPA_VSSR#4 DP/DPA_VSSR#5

DPCD/DPD_VDD18#1 DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1 DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1 DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1 DPAB/DPB_VDD10#2

AN34 AP39 AR39 AU37

DP/DPD_VSSR#1 DP/DPD_VSSR#2 DP/DPD_VSSR#3 DP/DPD_VSSR#4 DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1 DP/DPB_VSSR#2 DP/DPB_VSSR#3 DP/DPB_VSSR#4 DP/DPB_VSSR#5

DPAB_CALR

DP E/F POWER DPEF/DPE_VDD18#1 DPEF/DPE_VDD18#2

DP PLL POWER DPAB_VDD18/DPA_PVDD DP_VSSR/DPA_PVSS

DPEF/DPE_VDD10#1 DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1 DP/DPE_VSSR#2 DP/DPE_VSSR#3 DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD DP_VSSR/DPD_PVSS +DPEF_VDD18

+1.0VSG

L80 VGA@ BLM18AG121SN1D_0603 2 1

470ohm/1A

2

1

2

AF34 AG34

DPEF/DPF_VDD18#1 DPEF/DPF_VDD18#2 DPEF_VDD18/DPE_PVDD DP_VSSR/DPE_PVSS

+DPEF_VDD10

AK33 AK34

+DPAB_VDD10

2


AP25 AP26

AF39 AH39 AK39 AL34 AM34 R379 2 VGA@ 1 AM39

2

+1.8VSG

+DPAB_VDD18

+DPAB_VDD10

AN33 AP33

220mA

2


2

1

2

1

2

L66 VGA@ BLM18AG121SN1D_0603 1 +1.0VSG

470ohm/1A

C

R377 150_0402_1% 1 VGA@ 2

AW28

AU28 AV27

+DPAB_VDD18

AV29 AR28

+DPAB_VDD18

AU18 AV17

+DPCD_VDD18

AV19 AR18

+DPCD_VDD18

AM37 AN38

+DPEF_VDD18

AL38 AM35

+DPEF_VDD18

DP/DPF_VSSR#1 DP/DPF_VSSR#2 DP/DPF_VSSR#3 DP/DPF_VSSR#4 DP/DPF_VSSR#5

DPEF_CALR

150_0402_1% 2160809000A11SEYMOU_FCBGA962

Seymour@

A

VSS_MECH#1 VSS_MECH#2 VSS_MECH#3

A39 AW1 AW39

Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title

Vancouver_Power/GND



Rev 1.0


Seymour@

Date:

5

2

470ohm/1A

B

DPEF/DPF_VDD10#1 DPEF/DPF_VDD10#2 DPEF_VDD18/DPF_PVDD DP_VSSR/DPF_PVSS

C446 VGA@ 1U_0402_6.3V4Z

1

C445 VGA@ 0.1U_0402_16V4Z

2

C444 VGA@ 10U_0603_6.3V6M

1

240mA

AP31 AP32

1

R376 150_0402_1% 2 VGA@ 1 L67 VGA@ BLM18AG121SN1D_0603 2 1

AP14 AP15

DP/DPC_VSSR#1 DP/DPC_VSSR#2 DP/DPC_VSSR#3 DP/DPC_VSSR#4 DP/DPC_VSSR#5

DPAB/DPA_VDD10#1 DPAB/DPA_VDD10#2

1

C440 VGA@ 10U_0603_6.3V6M

2

AP22 AP23

DPCD/DPC_VDD10#1 DPCD/DPC_VDD10#2

1

C439 VGA@ 1U_0402_6.3V4Z

2

1

AP13 AT13 AN17 AP16 AP17 AW14 AW16

C437 VGA@ 1U_0402_6.3V4Z

2

1

C436 VGA@ 0.1U_0402_16V4Z

1

+DPAB_VDD18

C438 VGA@ 0.1U_0402_16V4Z

470ohm/1A

DPAB/DPA_VDD18#1 DPAB/DPA_VDD18#2

L63 VGA@ BLM18AG121SN1D_0603 2 1

300mA 1

+DPCD_VDD18 L64 VGA@ BLM18AG121SN1D_0603 2 1

DPCD/DPC_VDD18#1 DPCD/DPC_VDD18#2

AN24 AP24

C434 VGA@ 1U_0402_6.3V4Z

2

+DPCD_VDD18

D

DP A/B POWER

C433 VGA@ 0.1U_0402_16V4Z

2

1

AP20 AP21

C432 VGA@ 10U_0603_6.3V6M

2

1

C431 VGA@ 1U_0402_6.3V4Z

1

C430 VGA@ 0.1U_0402_16V4Z

GND GND#100 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#152 GND#162

A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13

C441 VGA@ 10U_0603_6.3V6M

A

GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60 GND/PX_EN#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98

C435 VGA@ 10U_0603_6.3V6M

B

F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 @ 1 2 V13 R455 0_0603_5%

PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35

C429 VGA@ 10U_0603_6.3V6M

C

AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39

4

3

2


Sheet 1

22

of

47

5

4

3

U6 VREFCB_A1 M8 VREFDB_Q1 H1 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13

D

<20> B_BA0 <20> B_BA1 <20> B_BA2

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7

MDB26 MDB28 MDB27 MDB31 MDB25 MDB30 MDB24 MDB29

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

D7 C3 C8 C2 A7 A2 B8 A3


VDD VDD VDD VDD VDD VDD VDD VDD VDD

B2 D9 G7 K2 K8 N1 N9 R1 R9

VREFCA VREFDQ

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

M2 N8 M3

BA0 BA1 BA2

CLKB0 CLKB0# <20> CKEB0 <20> MAB[13..0]

ODTB0_1 <20> <20> <20> <20>

<20> DQMB#[7..0]

CSB0#_0 RASB0# CASB0# WEB0#

J7 K7 K9

CK CK CKE/CKE0

K1 L2 J3 K3 L3

ODT/ODT0 CS/CS0 RAS CAS WE

QSB3 QSB1

F3 C7

DQMB#3 DQMB#1

E7 D3

QSB#3 QSB#1

G3 B7

VREFCB_A2 M8 VREFDB_Q2 H1 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

B_BA0 B_BA1 B_BA2

M2 N8 M3

BA0 BA1 BA2

CLKB0 CLKB0# CKEB0

J7 K7 K9

CK CK CKE/CKE0

K1 L2 J3 K3 L3


DQSL DQSU

ODTB0_1 CSB0#_0 RASB0# CASB0# WEB0#

A1 A8 C1 C9 D2 E9 F1 H2 H9

VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

+1.5VSG

QSB2 QSB0

F3 C7

DQMB#2 DQMB#0

E7 D3

QSB#2 QSB#0

G3 B7

1

U8


+1.5VSG

MDB[0..63]

<20> MDB[0..63]

2

U7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

E3 F7 F2 F8 H3 H8 G2 H7



D7 C3 C8 C2 A7 A2 B8 A3



B2 D9 G7 K2 K8 N1 N9 R1 R9

VREFCB_A3 M8 VREFDB_Q3 H1 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13


B_BA0 B_BA1 B_BA2

M2 N8 M3

BA0 BA1 BA2

CLKB1 CLKB1#

J7 K7 K9

CK CK CKE/CKE0


K1 L2 J3 K3 L3


DQSL DQSU

<20> CKEB1 ODTB1_1

A1 A8 C1 C9 D2 E9 F1 H2 H9

<20> <20> <20> <20>

CSB1#_0 RASB1# CASB1# WEB1# QSB4 QSB5

F3 C7

DQMB#4 DQMB#5

E7 D3

QSB#4 QSB#5

G3 B7


E3 F7 F2 F8 H3 H8 G2 H7



D7 C3 C8 C2 A7 A2 B8 A3



B2 D9 G7 K2 K8 N1 N9 R1 R9

VREFCA VREFDQ


+1.5VSG

+1.5VSG

U9 VREFCB_A4 M8 VREFDB_Q4 H1 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13



B_BA0 B_BA1 B_BA2

M2 N8 M3

BA0 BA1 BA2

CLKB1 CLKB1# CKEB1

J7 K7 K9

CK CK CKE/CKE0

ODTB1_1 CSB1#_0 RASB1# CASB1# WEB1#

K1 L2 J3 K3 L3


+1.5VSG

DQSL DQSU

+1.5VSG

A1 A8 C1 C9 D2 E9 F1 H2 H9


VREFCA VREFDQ

QSB6 QSB7

F3 C7

DQMB#6 DQMB#7

E7 D3

QSB#6 QSB#7

G3 B7


E3 F7 F2 F8 H3 H8 G2 H7



D7 C3 C8 C2 A7 A2 B8 A3



B2 D9 G7 K2 K8 N1 N9 R1 R9

D

+1.5VSG


DQSL DQSU

+1.5VSG

A1 A8 C1 C9 D2 E9 F1 H2 H9

<20> QSB[7..0]

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

RESET

L8

B1 B9 D1 D8 E2 E8 F9 G1 G9

ZQ/ZQ0

J1 L1 J9 L9

R81 VGA@ 243_0402_1%

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 X76@ +1.5VSG

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

R103 VGA@ 56_0402_1% 2

1

R104 VGA@ 56_0402_1% 2

VGA@ 2

2

2

VREFCB_A3 1

R78 VGA@ 4.99K_0402_1%

C173 VGA@ 2

VREFDB_Q3 1

1

C172

1

1

VREFDB_Q2 1

R100 VGA@ 4.99K_0402_1%

1

R89 VGA@ 4.99K_0402_1%

C174 VGA@ 2

2

2

VGA@ 2

R98 VGA@ 4.99K_0402_1%

R88 VGA@ 4.99K_0402_1%

2

C171

2

1

VREFCB_A2 1

R97 VGA@ 4.99K_0402_1%

1

1

1 2

2

2

1

R87 VGA@ 4.99K_0402_1%

R90 VGA@ 4.99K_0402_1%

B

VREFCB_A4 1

R101 VGA@ 4.99K_0402_1%

C175 VGA@ 2

R102 VGA@ 4.99K_0402_1%

VREFDB_Q4 1 C176 VGA@ 2

+1.5VSG +1.5VSG +1.5VSG

2

1

2

1

2

1

2

C197 VGA@ 1U_0402_6.3V6K

2

+1.5VSG

1

C196 VGA@ 1U_0402_6.3V6K

1

C195 VGA@ 1U_0402_6.3V6K

2

C194 VGA@ 1U_0402_6.3V6K

2

1

C193 VGA@ 1U_0402_6.3V6K

2

1

C192 VGA@ 1U_0402_6.3V6K

2

1

C191 VGA@ 1U_0402_6.3V6K

2

1

C190 VGA@ 1U_0402_6.3V6K

1

C189 VGA@ 1U_0402_6.3V6K

2

C188 VGA@ 1U_0402_6.3V6K

2

1

C187 VGA@ 1U_0402_6.3V6K

2

1

C186 VGA@ 1U_0402_6.3V6K

2

1

C185 VGA@ 1U_0402_6.3V6K

2

1

C184 VGA@ 1U_0402_6.3V6K

2

1

C183 VGA@ 1U_0402_6.3V6K

2

1

C182 VGA@ 1U_0402_6.3V6K

2

1

C181 VGA@ 1U_0402_6.3V6K

2

1

C180 VGA@ 1U_0402_6.3V6K

2

1

C179 VGA@ 1U_0402_6.3V6K

+1.5VSG

2

1

2

A


Compal Secret Data


2

1

C206 VGA@ 10U_0603_6.3V6M

2

1

C205 VGA@ 10U_0603_6.3V6M

2

1

C204 VGA@ 10U_0603_6.3V6M

2

1

VRAM P/N : Samsung : SA00004GS10 (S IC D3 64M16 K4W1G1646G-BC11 FBGA) 900MHz Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )800MHz Hynix : SA000041S40 ( S IC D3 64MX16 H5TQ1G63DFR-11C FBGA )900MHz

C203 VGA@ 10U_0603_6.3V6M

2

1

C202 VGA@ 10U_0603_6.3V6M

2

1

C201 VGA@ 10U_0603_6.3V6M

2

1

C200 VGA@ 10U_0603_6.3V6M

1

C199 VGA@ 10U_0603_6.3V6M

<20> CLKB1#

R106 VGA@ 56_0402_1% 1 2

C198 VGA@ 0.01U_0402_25V7K

<20> CLKB1

R105 VGA@ 56_0402_1% 1 2

1

C178 VGA@ 1U_0402_6.3V6K

1

2

A

2

+1.5VSG

C177 VGA@ 0.01U_0402_25V7K

<20> CLKB0#

1

VGA@ 2

B1 B9 D1 D8 E2 E8 F9 G1 G9

0.1U_0402_16V4Z

<20> CLKB0

VGA@ 2


+1.5VSG

0.1U_0402_16V4Z

ODTB1_1

VREFDB_Q1 1 C170


+1.5VSG

0.1U_0402_16V4Z

R95 VGA@ 4.99K_0402_1%

R96 VGA@ 4.99K_0402_1%

ZQ/ZQ0


0.1U_0402_16V4Z

<20> ODTB1

1

1

1

VREFCB_A1 1 C169

R86 VGA@ 4.99K_0402_1%

0.1U_0402_16V4Z

R94 VGA@ 56_0402_1% 2

0_0402_5% VGA@ ODTB1 R93 0_0402_5%

R82 VGA@ 243_0402_1%

RESET

+1.5VSG

0.1U_0402_16V4Z

1

R83 VGA@ 4.99K_0402_1%

0.1U_0402_16V4Z

R92 VGA@ 56_0402_1% 2

0.1U_0402_16V4Z

1

J1 L1 J9 L9

96-BALL SDRAM DDR3 K4B1G1646E-HC12_FBGA96 X76@

R85 VGA@ 4.99K_0402_1%

1

VGA@ ODTB0 R91

2

<20> ODTB0

2

B

R84 VGA@ 4.99K_0402_1%

T2 L8

B1 B9 D1 D8 E2 E8 F9 G1 G9


+1.5VSG ODTB0_1

VRAM_RST#

C

2

+1.5VSG

T2

1


+1.5VSG


VRAM_RST#

DQSL DQSU

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

2

R80 VGA@ 243_0402_1%

J1 L1 J9 L9

ZQ/ZQ0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

1

B1 B9 D1 D8 E2 E8 F9 G1 G9

RESET

DQSL DQSU

DML DMU

2


2

R79 VGA@ 243_0402_1%


L8

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9


1

J1 L1 J9 L9

VRAM_RST# T2

DML DMU

2

1

ZQ/ZQ0

DQSL DQSU

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

1

RESET

L8


2

T2

DML DMU

1

DQSL DQSU

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

2

VRAM_RST#

<20> VRAM_RST#


1

<20> QSB#[7..0]

DML DMU

2

C

2010/08/20

2011/08/20

Deciphered Date

Title

VRAM_DDR3 / Channel B


Rev 1.0


Date:

5

4

3

2


Sheet 1

23

of

47

4

Power Sequence of Whistler and Seymour

(JUMP form +3VS)

VGA_ON

10ms

VGA_PWR_ON

+3VSG

1.5_VDDC_PWREN

+VGA_CORE

+VGA_CORE

VDDCI

+1.5VSG

+1.5VSG

+1.0VSG

+1.0VSG

+1.8VSG

+1.8VSG

20ms

20ms

For PX sequence, >1mS delay is required between PE_GPIO1 and VGA_PWR_ON

VGA Muxless with BACO Status Mapping table Normal mode BACO mode PX_EN 0 1 1.5_VDDC_PWREN 1 0 VDDC_EN 1 0 1.0_EN 0 1 +3.3VSG ON ON +1.8VSG ON ON +1.0VSG ON ON +VGA_CORE ON OFF +1.5VSG ON OFF +BIF_VDDC +VGA_CORE +1.0VSG

WOBACO@ R107 1 2 0_0402_5% +3VS

PE_GPIO1 C

+3VS

2

R108 1

B

Y

2 10K_0402_5% 1

A

BACO@

I

2

O

3

7 1

1 3

S

O

1 4

Q2 BACO@ 2N7002_SOT23 +5VS

1 VAN@ 2 R170 0_0402_5%

For DVT 1011

9

1

O

8

7

1

B

S

30mil

+VGA_CORE WOBACO@ 1 2 R117 0_0805_5%

Change 0603 size For DVT 2 G

VDDC_EN

C214 0.1U_0402_16V4Z @

30mil

3 +VGA_CORE

Q9 PX@

1 BACO@

1

3 BACO@

S

1

+BIF_VDDC

Q7 AO3416_SOT23-3

Q8 AO3416_SOT23-3

2011/08/20

Title

AO3416 NMOS Vgs(th)(Max)= 1V Rds(on)(Max)= 22m ohm @Vgs=4.5V

A

2 G 2N7002_SOT23 S 3

VAN@2 1 R122 0_0402_5% 1 MAN@ 2 R123 0_0402_5%

2

1 1 C212 C239 BACO@ BACO@ 10U_0603_6.3V6M 2 2 10U_0603_6.3V6M

2 G

2

VGA_PWR_ON <25,35> 2

D

MAN_GPIO1_DELAY

3 BACO@

For VGA Power on control

D

PX@ 2 1 R120 0_0402_5%

2

12

S

VAN_GPIO1_DELAY

1

D

2 14

O G

I

A

D

1 BACO@

1.0_EN

7

7

3

2 G 2N7002_SOT23 S

VGA@ U11F SN74LVC14APWLE_TSSOP14

P

14

P

13

G

2 C213 VGA@ 0.1U_0402_16V4Z 1

10

3

20mil

1

1 2 1

O

D

I

Q5 AO3416_SOT23-3

AO3416_SOT23-3

G

PX@ 2 0_0402_5%

1 R121

C211 VGA@ 2 0.1U_0402_16V4Z

VGA@ U11E SN74LVC14APWLE_TSSOP14

+1.0VSG R116 0_0402_5% DISO@

G

<35> PE_GPIO1#

P


For DVT 1011

+3VALW

1

11 Q6 PX@

G

4

From +VGA_CORE regulator

S

+3VALW

R118 31.6K_0402_1% @

D

5

1 MAN@ 2 R171 0_0402_5%

Q4

R119 PX@ 10K_0402_1% 1 2

4

Y A

MAN_GPIO1_DELAY

+3VS

<13,35> PE_GPIO1

B

3

14 I

G

2

6

O 7

C210 VGA@ 0.1U_0402_16V4Z

I

G

5

1 BACO@ 2 2 R114 0_0402_5% 1

P

14 P 1 MAN@ 2 R115 0_0402_5%

<13,43> VGA_PWRGD

Q3A BACO@ DMN66D0LDW-7_SOT363-6

Delay EC_PWROK 50ms

U12 BACO@

Q3B BACO@ DMN66D0LDW-7_SOT363-6

1.5_VDDC_PWREN VGA@ U11D SN74LVC14APWLE_TSSOP14

VDDC_EN 1.0_EN

+3VALW

B

<31> INT_VGAPWR_ON

R113 BACO@ 1K_0402_5%

+3VS

5

C209 BACO@ 0.1U_0402_10V7K 2 1

VGA@ U11C SN74LVC14APWLE_TSSOP14

+5VS

R112 BACO@ 1K_0402_5%

VAN_GPIO1_DELAY

+3VALW

1.5_VDDC_PWREN <35,43>

2

14 I

G

2

G

1

C208 VGA@ 0.1U_0402_16V4Z

VGA@ U11B SN74LVC14APWLE_TSSOP14

7

1 VAN@ 2 R111 0_0402_5%

<31,35> VGA_ON

R110 5.11K_0402_1% BACO@

1.5_VDDC_PWREN

P

14

VGA@ U11A SN74LVC14APWLE_TSSOP14

P

Delay SUSP# 10ms

+3VALW

D

1 BACO@ 2 2 R77 0_0402_5% G

<22> PX_EN

4


3

VGA Power ON Circuit +3VALW

P

VGA_PWR_ON

C

U10 BACO@

5

>1ms

C207 BACO@ 0.1U_0402_10V7K 1 2

G

VGA_PWR_ON

D

VGA Power Enable Signal Mapping table Graville Whistler and Seymour VGA_PWR_ON source signal INT_VGAPWR_ON VGA_ON VGA_PWR_ON SUSP# +3.3VSG VGA_PWR_ON VGA_PWR_ON +1.8VSG VGA_PWR_ON VGA_PWR_ON +1.0VSG +VDDCI VGA_PWR_ON Combine with +VGA_CORE VGA_PWR_ON 1.5_VDDC_PWREN +VGA_CORE VGA_PWR_ON 1.5_VDDC_PWREN +1.5VSG

2

VGA_PWR_ON

1

50ms

6

Ref CLK INT_VGAPWR_ON D

VGA_PWR_ON 1.5_VDDC_PWREN +3.3VSG +1.8VSG +1.0VSG +VGA_CORE +1.5VSG +BIF_VDDC

SUSP# +3VSG

2

38ms

1

1

FCH_PWRGD

2

VGA Muxless and Dis only Status Mapping table Muxless Power-saving GPU Dis only Muxless High performance GPU 1 1 0 1 1 0 ON ON OFF ON ON OFF ON OFF ON ON ON OFF ON ON OFF +VGA_CORE +VGA_CORE OFF

3

Power Sequence of Granville

3

1

5

Issued Date


Compal Secret Data


Deciphered Date

VGA power sequence and BACO


Rev 1.0


Date:

5

4

3

2


Sheet 1

24

of

47

3

2

+3.3VS TO +3.3VSG

1

1.05VS TO +1.0VSG

Change P/N SB548000210 +1.05VS

D

S SSM3K7002FU_SC70-3

ACIN

<31,35,37> ACIN

4 2 D

S

2 VGA_PW R_ON# G Q11 VGA@ 2N7002_SOT23

S

1

D

VGA_PW R_ON# 2 VGA@ 1 2 G R131 100K_0402_5% Q14 S 1 2N7002_SOT23 C223 VGA@ VGA@ 2 0.1U_0603_25V7K

510K_0402_5%

VGA_PW R_ON# <35>

1.0VSG_GATE

@ R132 1

S

MAN@ 2 VGA_PW R_ON# G Q12 2N7002_SOT23

2

D

R125 VGA@ 470_0603_5%

3

2 VGA@ 1 R129 10K_0402_5% 1

1

MAN@ Q13

1 1 C215 VGA@ 10U_0603_6.3V6M C217 2 2 VGA@ 1U_0402_6.3V4Z

Change 0603 size For DVT +VSB

D

1

C218

VGA@ VGA@ 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M

R127 470_0603_5% MAN@

1

10U_0603_6.3V6M 2

1

3

C222 MAN@ 2 0.1U_0603_25V7K

C220

3

1

D

2 G

1

3

2

1 1

1 2 R128 33K_0402_5% MAN@

MAN@ VGA_PW R_ON 1 2 10K_0402_5% R130

C216

2

2

MAN@ 3VSG_GATE

R126 MAN@ 100K_0402_5%

G

<24,35> VGA_PW R_ON


D

S

C219 1 MAN@ 0.1U_0603_25V7K 2 3VSG_GATE


1

1 VAN@ 2 R124 0_0805_5% Q10 SI2301CDS-T1-GE3_SOT23-3 MAN@ 3 1

D

+1.0VSG U13 VGA@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5

2

+3VSG

3

+3VS

1

4

1

5

C221 VGA@ 0.1U_0603_25V7K

2N7002_SOT23 VGA@ Q15

2 G

C

C

+1.8VS TO +1.8VSG

Change P/N SB548000210

2 1 1 C227 VGA@ 10U_0603_6.3V6M C228 2 2 VGA@ 1U_0402_6.3V4Z

Change 0603 size For DVT 1.5_VDDC_PW REN#

<35>

+VSB

1.8VSG_GATE 2 VGA@ 1 R135 100K_0402_5% D

VGA_PW R_ON# 2 VGA@ 1 2 G R137 100K_0402_5% Q18 S 1 2N7002_SOT23 C234 VGA@ VGA@ 2 0.1U_0603_25V7K ACIN 2 G

1

D

S

D

S

1

2

2 VGA_PW R_ON# G Q16 VGA@ 2N7002_SOT23

C232 VGA@ 0.1U_0603_25V7K

B

Q20 VGA@ 2N7002_SOT23

3

1

2

3

3

VGA@ R140 C233 1.5_VDDC_PW REN# 2 VGA@ 1 VGA@ VGA@ 2 G R139 47K_0402_5% 510K_0402_5% 0.1U_0603_25V7K 2 Q19 S 1 2N7002_SOT23 C235 VGA@ D 0.1U_0603_25V7K Q21 2 ACIN 2 VGA@ G 2N7002_SOT23 S

R134 VGA@ 470_0603_5%

3

2 1.5_VDDC_PW REN# G Q17 2N7002_SOT23 VGA@

510K_0402_5%

S

1

1

D

VGA@ VGA@ 2 2 10U_0603_6.3V6M 10U_0603_6.3V6M

@ R138 1

1.5VSG_GATE 1 VGA@ 2 R136 100K_0402_5%

1

D

3

+VSB B

C229

2


1

4

2

2 10U_0603_6.3V6M

C226 R133 VGA@ 470_0603_5%

1

VGA@

C225 VGA@ 1U_0402_6.3V4Z 2

1

10U_0603_6.3V6M

C231

C224 VGA@ 10U_0603_6.3V6M 2

1

1

2

1

Change 0603 size For DVT 1

+1.8VSG U15 VGA@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5

1

C230 VGA@

1

U14 VGA@ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5

4


+1.5VSG

3

+1.5V

+1.8VS

1


1

+1.5V TO +1.5VSG

A

A


Compal Secret Data


Issued Date

Deciphered Date

2011/08/20


4

3

2

Title

VGA DC Interface Size Document Number Custom

Rev 1.0


Date: Monday, November 29, 2010

Sheet 1

25

of

47

4

3

U70 C907 1

<13> PCIE_FRX_DTX_P2

C908 1

2

0.1U_0402_16V4Z

2

0.1U_0402_16V4Z

PCIE_FRX_C_DTX_N0 PCIE_FRX_C_DTX_P0

<13> PCIE_FTX_C_DRX_N2

CLK_PCIE_LAN# CLK_PCIE_LAN

<13> CLK_PCIE_LAN# <13> CLK_PCIE_LAN R909 1

<13,18,29> PLT_RST#

R1143 1 R1144 1

<14,29> FCH_PCIE_WAKE# <31> EC_PME#

+3V_LAN 1 R1148 1 R1150 1 R1152

@

TX_P

36

RX_N

32 33

2 0_0402_5% @

2 0_0402_5% 2 0_0402_5%

LAN_PME#

1 C1475

1 C1476

1 C1477

1 C1478

REFCLK_N REFCLK_P

WAKE#

7 8

1 C1479

RX_P

3

8151@ LAN_CLKREQ# 1 R1155 2 0_0402_5% 1.8V_VDDCT_REG 4 <14> LAN_CLKREQ# 8152@ 0.1U_0402_16V4Z 1 2 C1474 13 19 31 34 W=30mils +1.1_AVDDL 6 1

41 C1480

LAN_X11

Y6 2

close to pin34

LAN_ACTIVITY LAN_LINK# LED2_CKR#

TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3

12 11 15 14 18 17 21 20

LAN_MDI0LAN_MDI0+ LAN_MDI1LAN_MDI1+ LAN_MDI2LAN_MDI2+ LAN_MDI3LAN_MDI3+

RBIAS

TEST_RST TESTMODE

VDD33 LX

XTLO XTLI

Close LAN chip

LAN_CLKREQ# 1 2 R1139 8152@ 0_0402_5%

LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3-

1@

2 C1466 1000P_0402_50V7K

1

2 C1467 0.1U_0402_16V4Z

1@

2 C1468 1000P_0402_50V7K

VDDCT CLKREQ# DVDDL DVDDL_REG AVDDL AVDDL AVDDL AVDDL AVDDL_REG

AVDDH AVDDH AVDDH_REG

overclocking

0*

Un-overclocking

1*

SWR mod

0

1

2 C1469 0.1U_0402_16V4Z

LDO mode

1@

2 C1470 1000P_0402_50V7K

1

2 C1471 0.1U_0402_16V4Z

1@

2 C1472 1000P_0402_50V7K

1

2 C1473 0.1U_0402_16V4Z

LAN_LINK# * default

D

8151@

8151@

R1146 keep away other singal (25mil) 1

1 LAN_ACTIVITY

R1140 49.9_0402_1% 1 2 R1142 49.9_0402_1% 1 2 R1145 49.9_0402_1% 1 2 R1147 49.9_0402_1% 1 2 R1149 49.9_0402_1% 1 8151@ 2 R1151 49.9_0402_1% 1 8151@ 2 R1153 49.9_0402_1% 1 8151@ 2 R1154 49.9_0402_1% 1 8151@ 2

LAN_MDI0+

R1146 2.37K_0402_1% 2 1

10

1

+3V_LAN

40

LX

W=40mils

W=40mils

1

+1.7V_VDDCT

5

W=40mils L108

LX

+1.7V_VDDCT

2

4.7UH_PG031B-4R7MS_1.1A_20% 24 37

+1.1V_DVDDL

1 C1481

W=30mils

1 C1482

0.1U_0402_16V4Z 2 16 R1156 1 8151@ 2 0_0603_5% +2.7V_AVDDH 22 9

close to Lan pin5

2

1 C1484

C1483

1000P_0402_50V7K0.1U_0402_16V4Z 1 2

+2.7V_AVDDH

+1.1V_DVDDL

C1494 1

AR8152-AL1E

SA00003JW10

C1495

1

1U_0402_6.3V6K 2 2

close to pin6

close to Lan pin40

W=30mils

W=30mils

8152@

8151@

PN:SA00003LE30 PN:SA00003JW10

10U_0603_6.3V6M 2

W=30mils

U70

GND

AR8151-AL1B AR8152-AL1E

close to pin31

close to pin19

38 39 23

AR8151-AL1A_QFN40_5X5

2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

close to pin13

LED_0 LED_1 LED_2

SMCLK SMDATA

8151@ 2 8151@ 2 2

C

8151-AL1A

PERST#

28 27 LAN_X2 LAN_X1

Atheros

2

25 26

PLT_RST# 2 4.7K_0402_5% LAN_PME# 2 4.7K_0402_5% LAN_CLKREQ# 2 4.7K_0402_5%

TX_N

30

35

<13> PCIE_FTX_C_DRX_P2

D

29

Pin23 Function: 1.CLKREQ 2.AR8152L revA PH:

LAN_X2

1 C1496 2

0.1U_0402_16V4Z

<13> PCIE_FRX_DTX_N2

2

R1138 5.1K_0402_5% 1 2

0.1U_0402_16V4Z

5

1

C1487

1

C1488

1

1

C

C1489

C1497 1U_0402_6.3V6K 0.1U_0402_16V4Z 2 2

8151@ 2

0.1U_0402_16V4Z 2

0.1U_0402_16V4Z

W=40mils

2 C1485 33P_0402_50V8K

1

1

2

25MHZ_20PF_7A25000012 C1486 33P_0402_50V8K

close to Lan pin9

close to Lan pin22

close to Lan pin16

close to Lan pin37

close to Lan pin24

+3V_LAN +3VALW

Change Y6 P/N as SJ100003300

R1157 1

1A

2 0_0603_5% C1490 1

Follow result by vender 10/11

C1491 1

C1492 1

C1493 1 JRJ45

2

1

10

R1159 8152@

1

close to Pin 1 BOTH_TST1284

2

SP050001X10

LAN_MDI0+ LAN_MDI0-

10 11 12

24 23 22

RJ45_MDI3+ RJ45_MDI3-

TCT2 TD2+ TD2-

MCT2 MX2+ MX2-

21 20 19


TCT3 TD3+ TD3-

MCT3 MX3+ MX3-

TCT4 TD4+ TD4-

MCT4 MX4+ MX4-

LAN_ACTIVITY

18 17 16


15 14 13


LAN_ACTIVITY LAN_LINK#

LANGND

2

RJ45_MDI1+

3

RJ45_MDI2+

4

RJ45_MDI2-

5

RJ45_MDI1-

6

RJ45_MDI3+

7

RJ45_MDI3-

8


PR2+

R456 0_0805_5%

PR3+

PR2PR4+ PR4-

11

Yellow LED+

12

Yellow LEDSANTA_130451-K CONN@

RJ45_GND

1

LANGND

2

1

1

1

1

1

1

1 1 @ @ C942 C939 L109 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 2 2

D49 @ B88069X9231T203_4P5X3P2-2

100UH +-20% SSC0301101MCF 0.18A

2

A

2

2

2

40mil

40mil

RJ45_GND

2

C941 1000P_1206_2KV7K @

1

Security Classification @ 1 D48 Issued Date B88069X9231T203_4P5X3P2-2

8151@

Populate when AR8151-AL1A

8152@

Populate when AR8152-AL1E

EMI Request for MP

Compal Secret Data 2010/08/20

2011/08/20

Deciphered Date

Title

Compal Electronics, Inc. LAN AR8151 / AR8152


Rev 1.0


EMI Request for MP 5

4

B

PR3-

C940 1000P_1206_2KV7K

Place close to TCT pin

14 13

SHLD1 SHLD2

PR1-

1

1

R1161 511_0402_1%

1

PR1+

@ 470P_0402_50V7K 2 D47 PJDLC05C_SOT23-3 @

2

close to pin7 close to pin10

2 C1499

R819 75_0402_1% 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 75_0402_1% R820 8151@ 1 1 1 1 1 1 1 1 1 C1503 C1504 C1505 C1506 C1507 C1508 C1509 C1510 C1511 @ @ 8151@ @ 8151@ @ @ R821 R822 1U_0402_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% 2 2 2 2 2 2 2 2 2 8151@

close to pin4

1

RJ45_MDI0-

Green LED-

2

LAN_MDI1+ LAN_MDI1-

7 8 9

close to pin1

RJ45_MDI0+

EMI Request for MP

Green LED+

2

LAN_MDI2+ LAN_MDI2-

4 5 6

MCT1 MX1+ MX1-

TCT1 TD1+ TD1-

3

1 2 3

350UH_IH-037-2 8151@

A

C1498 @ 470P_0402_50V7K

1

LAN_MDI3+ LAN_MDI3-

2

+1.7V_VDDCT

0_0603_5% 1 2 R1160

511_0402_1%

T25

3

B

9

2

LAN_LINK#

2 0_0402_5%

2

T25

R1158 1

+3V_LAN

1

2 2 2 2 10U_0603_6.3V6M 1U_0402_6.3V6K 10U_0603_6.3V6M 0.1U_0402_16V4Z

Date:

3

2

Monday, November 29, 2010

Sheet 1

26

of

47

A

B

C

E

F

G

H

+5VS_AVDD

1

1

1

+3VS

D

R783 20K_0402_1%

D38

2

2

2

R789 10K_0402_5%

CH751H-40PT_SOD323-2

C936 1 1U_0402_6.3V4Z

1

2

C

R787

1

1

1 R786 2 15.4K_0402_1%

1

C952 1 1U_0402_6.3V4Z

<31> BEEP#

MONO_IN

2

2

Dos Beep issue for PVT 10/28

Q72

2 B

HD Audio Codec

E

3

560_0402_5%

2SC2411KT146_SOT23-3

2

R788

1

2

560_0402_5%

1

C946 1 1U_0402_6.3V4Z

<14> FCH_SPKR

D37 CH751H-40PT_SOD323-2

0_0603_5% 2

1

80mil

+3VS_DVDD 1 1 C1512 0.1U_0402_16V4Z C1513 C1514 10U_0603_6.3V6M 0.1U_0402_16V4Z 2 2 2


+3VS_AUX

10mil

2 34 41 42

+3VS_AUX

1 C1524

2 1U_0402_6.3V6K

1

Change 2.2u For DVT MIC1_L MIC1_R

2

<28> MIC1_R

1 C1520

22

2.2U_0603_6.3V6K MIC1_C_L 35

2

C932 1

MIC1_C_R 36 2.2U_0603_6.3V6K 37

2

+MIC1_BIASC

SPK_OUT_R+ PORTE_R SPK_OUT_RPORTF_L PORTB_L PORTF_R PORTB_R FLY_P

16

SPKL-

19

SPKR+

SPKL+ <28>

SPKR-

39

MIC2_C_L C794 1

40

MIC2_C_R

1 C797

38

RESET#

11

HDA_RST_AUDIO#

7

HDA_BITCLK_AUDIO

1

R1168 10K_0402_5%

MONO_IN 1

<31> EC_MUTE#

1

2

1

1

2

2

JUMP_43X39 @ J2 1 1 2 2

JUMP_43X39 @ J5 1 1 2 2

JUMP_43X39 @ J3 1 1 2 2

JUMP_43X39 @ J6 1 1 2 2

JUMP_43X39 @

GND

JUMP_43X39

DMIC_CLK0 DMIC_1/2

C1528

@

2 0_0402_5%

+AVEE 1 C1529

44 43

SENSE A SENSE B

47

GPIO0/EAPD#

48

SPDIFO

24 49

GPIO1/SPK_MUTE# GPIO2/SPDIF2

FILT_1.8

AVEE

FILT_1.65

EP_GND

AVDD_3.3

Change 2.2u & 100ohm For DVT

HDA_SDOUT_AUDIO <14> HDA_SYNC_AUDIO

Port Port Port Port Port Port Port Port Port

HDA_RST_AUDIO# <14> HDA_BITCLK_AUDIO <14>

L112 2

2 C948 22P_0402_50V8J

1

FBMA-10-100505-301T_2P 2

Pop For EMI 10/18

3

3 4

G1 G2

ACES_88266-02001 CONN@

D27 @ PJDLC05C_SOT23-3

3

A: B: C: D: E: F: G: J: H:

Headphone jack (jack shared with S/PDIF) Internal MIC (mono or stereo) Microphone/LI/LO jack Line Out jack (Optional) Line In jack (Optional) Not used. Internal stereo speakers Internal stereo digital mic (Optional) S/PDIF (jack shared with headphone)

46 45

10mil

5

30

1 C1525

+FILT_1.65V

32

10mil

+3VS_LDO_OUT

10mil 1 C1531

1

C1532

1 C1527

R1170

0.1U_0402_16V4Z 10U_0603_6.3V6M 10K_0402_5% 2 2 R1170 only needed if supply to VAUX_3.3 is removed during system re-start.

1 C1530

1U_0603_10V6K 2

+FILT_1.8 1 C1526

0.1U_0402_16V4Z 2


4

Change 0603 size For DVT Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title


GNDA B

1 2

Port Configuration

<14>

0.1U_0402_16V4Z 10U_0603_6.3V6M 2 2


1 1 220P_0402_50V7K 220P_0402_50V7K @ @ C979 C980 2 2

1 2

HDA_SDIN0 <14>

1

CX20584-11Z_QFN48_7X7

@

GNDA GND A

EXT_MUTE#

0.1U_0402_16V4Z 10U_0603_6.3V6M 2 2

J4

J1 2

12

15mil

2

SENSE_A

1 R796

<31> EAPD

1

PCBEEP

Mic issue For MP

EC_MUTE# change as Pin12

Sense resistors must be connected same power that is used for VAUX_3.3

1

2 0_0402_5%

R1169

DMIC_3/4

13

R797 2 0_0402_5%

INT_MIC 1 100_0402_1%

+MIC2_BIASC

HDA_SYNC_AUDIO

C_BIAS

C808 220P_0402_50V7K

SPKR- <28> 2 2.2U_0603_6.3V6K INT_MIC_22 R523 2 2.2U_0603_6.3V6K

10

PORTC_R

1

SPKR+ <28>

17

8

R800 2 0_0402_5%

SPKL- <28>

6

BIT_CLK

MIC_PLUG# <28>

2

JMIC2 SPKL+

SYNC

SDATA_OUT PORTC_L

2

1

INT_MIC1 14

1 2 R793 33_0402_5% HDA_SDOUT_AUDIO

SDATA_IN

Close to Conn

INT_MIC

2

SPK_OUT_LPORTE_L

HP_PLUG# <28>

1 C1523

3

PORTD_R

FLY_N

1 C1522


20

18

15

31

29

21

SPK_OUT_L+

B_BIAS 23

C934 1

PORTD_L

1 C1521

0.1U_0402_16V4Z 10U_0603_6.3V6M 2 2 2 2 0.1U_0402_16V4Z 10U_0603_6.3V6M

CLASSDREF

PORTA_R

RPWR5.0

26

LPWR5.0

PORTA_L

HP_RIGHT

AVDD_5V

25

AVDD_HP

HP_LEFT

33

<28> MIC1_L

1

40mil

28

R1166 5.11K_0402_1%

R585 2.2K_0402_5%

0.1U_0402_16V4Z 2 +CLASSD_REF

+3VS_AUX

27

4

+5VS

2 C1519

<28> HP_RIGHT

1

2 0_0603_5%

80mil

1 C1518 0.1U_0402_16V4Z 2

U82

2

1 R1164

1

1 C1516 1U_0402_6.3V6K 2

<28> HP_LEFT

SENSE_A

0_0603_5% 2

1

C1517 10U_0603_6.3V6M

9

2

DVDD_3.3

2

R1167 2 1 39.2K_0402_1%

R1162 1

+MIC2_BIASC

10U_0603_6.3V6M 0.1U_0402_16V4Z 2 2

+CLASSD_5V

4

1

VDD_IO

1 C1515 0.1U_0402_16V4Z


3

+5VS_AVDD 1 C1210 C1211

0.1_1206_1%

VAUX_3.3

2

1

R1163

+3VS_AUX 2 0_0402_5%

1 R1165

+3VS

1

1

1

2 R1093 +3VS

Layout Note: Path from +5V to LPWR_5.0 and RPWR_5.0 must be very low resistance ( <0.01 ohms). Place by caps very close to device.

Change 0603 size For DVT 20mil

HD Audio Codec CX20584 Document Number

Date:

C

D

E

F

Rev 1.0

LA-7092P P5WE6/H6/S6 Wednesday, November 24, 2010 G

Sheet

27 H

of

47

A

B

C

D

E

Int. Speaker Conn. 1

R834 1 R833 1

3

30mil

D39 2

2

C1533 C1534 @ 1000P_0402_50V7K 1 1 1000P_0402_50V7K

1 2

1 2

3 4

G1 G2

Left

ACES_88266-02001 CONN@

1

@

1

JSPK2

SPK_L+ SPK_L-

2 0_0603_5% 2 0_0603_5% 2

SPKL+ SPKL-

<27> SPKL+ <27> SPKL-

PJDLC05C_SOT23-3

JSPK1 R831 1 R832 1

@ @

SPK_R+ SPK_R-

2 0_0603_5% 2 0_0603_5% 3

30mil 2

D41 @

2

C1535 C1536 @ 1000P_0402_50V7K 1 1 1000P_0402_50V7K

1 2

3 4

G1 G2

Right

ACES_88266-02001 CONN@

1

@

1 2

2

SPKR+ SPKR-

<27> SPKR+ <27> SPKR-

PJDLC05C_SOT23-3

2

2

C779 330P_0402_50V7K

1

<27> HP_LEFT

R686 1

<27> HP_RIGHT

R685

HPOUT_L_1

2 39_0603_1% 2 39_0603_1%

HPOUT_R_1

1 L94 1 L93

2

1

2

C774

Headphone Out

330P_0402_50V7K 1

JHP1 1 2

HPOUT_L_2 2 FBMA-L11-160808-700LMT_2P HPOUT_R_2 2 FBMA-L11-160808-700LMT_2P

3 4

<27> HP_PLUG#

HP_PLUG#

5

6 SINGA_2SJ-0960-C01 CONN@

3

MIC_PLUG#

3

1

1 1

1 1

2

JMIC1

MIC1_R_R 1

C780 220P_0402_50V7K

1 2

MIC1_L_R

L89 1 2 FBMA-L11-160808-700LMT_2P L90 1 2 FBMA-L11-160808-700LMT_2P

2

2

3 3

1 R695

MIC1_L_1 2 100_0603_1% MIC1_R_1 2 100_0603_1%

MIC JACK

R693 3.01K_0402_1%

2 <27> MIC1_R

1

@ D24 PJDLC05C_SOT23-3

D42 CH751H-40PT_SOD323-2

R692 3.01K_0402_1%

R694

2

2

2

+MIC1_BIASC

D43 CH751H-40PT_SOD323-2

<27> MIC1_L

3

HP_PLUG# +MIC1_BIASC

1

2

C781 220P_0402_50V7K

@ D29 <27> MIC_PLUG#

4 MIC_PLUG#

5

PJDLC05C_SOT23-3 6

4

4

1

SINGA_2SJ-A960-C01 CONN@

2010/08/20

Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title


Date:

A

B

C

D

Amplifier & Audio Jack Document Number

Rev 1.0


Sheet E

28

of

47

A

B

C

D

E

Mini-Express Card for WLAN +3VS

1

2

+1.5VS

1

C705 4.7U_0603_6.3V6K

2

1

C706 0.1U_0402_16V4Z

2

1

C707 0.1U_0402_16V4Z

2

1

C708 4.7U_0603_6.3V6K


2

1

C709 0.1U_0402_16V4Z

2

C710 0.1U_0402_16V4Z

Change 0603 size For DVT JMINI1

R440 1

@

2 0_0402_5%

<14> MINI1_CLKREQ# <13> CLK_PCIE_MINI1# <13> CLK_PCIE_MINI1

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

<13> PCIE_FRX_DTX_N3 <13> PCIE_FRX_DTX_P3 <13> PCIE_FTX_C_DRX_N3 <13> PCIE_FTX_C_DRX_P3 +3VS

R445 1

E51TXD_P80DATA_R E51RXD_P80CLK

1 3 5 7 9 11 13 15

2 4 6 8 10 12 14 16

17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

+3VS

53 54 55 56

Mini Card Power Rating Power

WL_OFF# PLT_RST# +3V_WLAN

1 R441 1 R442 MINI1_SMBCLK 1 MINI1_SMBDAT R443 1 R444

@ @ @

WL_OFF# <31> PLT_RST# <13,18,26> +3VS +3VALW

2 2 0_0603_5% 0_0603_5% 2 0_0603_5% 2 0_0603_5%

FCH_SMCLK0 FCH_SMDAT0

USB20_N8 USB20_P8

1

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

+3V

330

250

250 (wake enable)

+1.5VS

500

375

Normal

5 (Not wake enable)

<8,9,14> <8,9,14>

<14> <14>

WIMAX_LED# WLAN_LED#_L

(MINI1_LED#)

+3VS

R835 1

+3VS ACES_88910-5204 CONN@

WIMAX_LED# @ 1 R836

2 10K_0402_5%

WLAN_LED#_L

0_0402_5% 2

R848 100K_0402_5%

2 1

MINI1_LED#

3 CHP202UPT_SOT323-3 D44 @ 1 2 R837 0_0402_5%

Height : 4mm

2

Primary Power (mA)

2

2 R492 100K_0402_5%

1

+1.5VS

G1 G2 G3 G3

<31> E51TXD_P80DATA <31> E51RXD_P80CLK

0_0402_5% 2

1 3 5 7 9 11 13 15

1

FCH_PCIE_WAKE#

<14,26> FCH_PCIE_WAKE#

1

<31>

(9~16mA) 2

Card Reader RTS5138 / RTS5137 (only SD+MMC function) Card Reader Connector

R854

2 0_0805_5%

1

2 C981 R855 1

1

USB20_N6 USB20_P6

30mil C984

1 0.1U_0402_16V4Z

1

2

RREF

+SDPWR_MMWR

+3VS_CR +CARDPWR VREG

10mil

C985 1U_0402_6.3V6K XDDRY_SDWP_MSCLK XDCE#_SDD1 XDCLE_SDD0

U84 1 2 3 4 5 6 7 8 9 10 11 12

5IN1_LED#

REFE GPIO0 DM DP

CLK_IN

3V3_IN CARD_3V3 V18

XD_D7

XD_CD# SP1 SP2 SP3 SP4 SP5

SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6

17

1 R856

24

@

2 10_0402_5% CLK_SD_48M_R

5IN1_LED# C982 1

<32>

2 10P_0402_50V8J

JCR1 XDD4_SDD3_MSD1 XDD2_SDCMD

@ 2 R857

1 22_0402_5%

CLK_SD_48M

<13>

1 2 3 4 5 6

23 XDD0_SDCLK_MSD2 22 21 20 19 18 16 15 14 13

XDD5_SDD2_MS_D5 XDD4_SDD3_MSD1 XDD2_SDCMD

+CARDPWR

+SDPWR_MMWR

30mil

1 R858

XDD0_SDCLK_MSD2 XDWE#_SDCD#

RTS5138-GR_QFN24_4X4

@

2 0_0805_5%

XDCLE_SDD0 XDCE#_SDD1 XDD5_SDD2_MS_D5 XDDRY_SDWP_MSCLK XDWE#_SDCD#

30mil

1

R859 100K_0402_5%

2

1

25


2

2

30mil 10mil

1 100P_0402_50V8J 2 6.2K_0603_1%

<14> USB20_N6 <14> USB20_P6

C983 4.7U_0603_6.3V6K

3

+3VS_CR

7 8 9 10 11

D3 CMD VSS1 VDD CLK VSS2 D0 D1 D2 WP CD

2

+3VS

EPAD

3

C986 0.1U_0402_16V4Z

C987 0.1U_0402_16V4Z

1

1

2

2

C988 0.1U_0402_16V4Z

C987, C988 close to connector

Change to RTS5137 (SA000043500)

12 13

GND1 GND2 TAITW_PSDBTC09GLBS1N14N0 CONN@

4

4

Compal Secret Data


2010/08/20

Deciphered Date

2011/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title Size

B

C

D

Document Number

Rev 1.0

LA-7092P P5WE6/H6/S6 Date:

A

Compal Electronics, Inc. MINI CARD / CardReader RTS5137 Wednesday, November 24, 2010 E

Sheet

29

of

47

A

B

C

D

E

F

G

H

SATA HDD Conn. JHDD1


SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0


1

1 2 3 4 5 6 7

SATA_ITX_DRX_P0 SATA_ITX_DRX_N0 C657 1 C659 1

2 0.01U_0402_16V7K 2 0.01U_0402_16V7K

SATA_DTX_IRX_N0 SATA_DTX_IRX_P0

GND A+ AGND BB+ GND

1

+3VS 1

2

R405 1

+5VS

0.1U_0402_16V4Z

+5VS_HDD

2 0_0805_5% 10U_0603_6.3V6M C660

1

2


C661

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

+3VS C639

0.1U_0402_16V4Z 1

C662

2

1

1

C663

2

1U_0402_6.3V4Z

2

V33 V33 V33 GND GND GND V5 V5 V5 GND Reserved GND V12 V12 V12

GND GND

24 23

SANTA_192301-1 CONN@

1000P_0402_50V7K

2

2

SATA ODD FFC Conn. JODD1 <15> SATA_ITX_DRX_P1 <15> SATA_ITX_DRX_N1 SATA_DTX_IRX_N1 SATA_DTX_IRX_P1 ODD_DA#_FCH_R

C650 1 2 0.01U_0402_16V7K C651 1 2 0.01U_0402_16V7K R412 1 @ 0_0402_5% 2 R403 1 @ 0_0402_5% 2

80mils +5VS

1 R955

+5VS_ODD 2 0_0805_5%

1 2 3 4 5 6 7 8 9 10 11 12

GND GND

13 14

2

<15> SATA_DTX_C_IRX_N1 <15> SATA_DTX_C_IRX_P1 <14> ODD_DA#_FCH <14> ODD_DETECT#

1 2 3 4 5 6 7 8 9 10 11 12

ACES_85201-1205N CONN@

1

R413 0_0402_5%

3

3

+5VS

+5VS_ODD

R760 470K_0402_5% @

@ 1

2

2

D Q66 SSM3K7002FU_SC70-3

@

S 1

@

3

2 G

1 @

2

C811 0.1U_0402_25V6K

<15> ODD_PWR

U40 @ SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5

R764 1.5M_0402_5%

1

ODD_EN

C812 1U_0402_6.3V6K

1

4

2

+VSB

4

4

Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title


HDD & ODD CONN Document Number

Date:

A

B

C

D

E

F

Rev 1.0

LA-7092P P5WE6/H6/S6 Wednesday, November 24, 2010 G

Sheet

30 H

of

47

5

4

3

2

1

For EC Tools

+3VALW L84

1

0.1U_0402_16V4Z 1 C725 1

0.1U_0402_16V4Z 1 2

C724

C726 KSO[0..17] <32>

KSI[0..7]

KSI[0..7]

2 2 0.1U_0402_16V4Z

2 2 0.1U_0402_16V4Z

C728 1000P_0402_50V7K 1 1

D

0.1U_0402_16V4Z

E51RXD_P80CLK E51TXD_P80DATA

ACES_85205-0400 @

67

9 22 33 96 111 125

65W /90W #

2

AVCC

R458 VR_ON

@ R489 10K_0402_5%

1

TP_CLK 2 4.7K_0402_5% TP_DATA 2 4.7K_0402_5%

1 R465 1 R466

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17

2

2

+3VALW +3VS

@ R852 0_0402_5%

1

1

@ R851 0_0402_5%

1 R467 1 R468

@ @

EC_SMB_CK2 2 2.2K_0402_5% EC_SMB_DA2 2 2.2K_0402_5%

+3VALW

B

1 R471 1 R472 1 R473 1 R474 2 R475 1 R476 2 R497

@ @

EC_SMB_CK1 2 2.2K_0402_5% EC_SMB_DA1 2 2.2K_0402_5% KSO1 2 47K_0402_5% KSO2 2 47K_0402_5% LID_SW # 1 100K_0402_5% EC_PME# 2 10K_0402_5% PBTN_OUT# 1 100K_0402_5%

<39> <39> <5,19> <5,19>

<14> SLP_S3# <14> SLP_S5# <14> EC_SMI# <10> LOCAL_DIM <29> MINI1_LED#

For LED INV_PWM freq to 1K ENBKL 1 100K_0402_5% LOCAL_DIM 1 100K_0402_5% COLOY_ENG_EN 1 100K_0402_5%

2 R488 2 R844 2 R845

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

<10> COLOY_ENG_EN <10> EC_INVT_PW M <34> FAN_SPEED1 <33> BT_ON# <34> ON/OFF <32> PW R_SUSP_LED <32> W LAN_LED#

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

77 78 79 80

SLP_S3# SLP_S5# EC_SMI# LOCAL_DIM MINI1_LED# COLOY_ENG_EN EC_INVT_PW M FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PW R_SUSP_LED W LAN_LED#

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

EC_CRY1 EC_CRY2

122 123

DAC_BRIG EN_DFAN1 IREF CALIBRATE#

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F

83 84 85 86 87 88

EC_MUTE#

SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0

97 98 99 109

3S/4S# 65W /90W # VLDT_EN LID_SW #

SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS#

119 120 126 128

CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59

73 74 89 90 91 92 93 95 121 127

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11

100 101 102 103 104 105 106 107 108

EC_RSMRST# EC_LID_OUT# EC_ON EC_SW I# EC_PW ROK_R BKOFF# W L_OFF#

PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

110 112 114 115 116 117 118

VGATE ENBKL EAPD EC_THERM# SUSP# PBTN_OUT# EC_PME#

V18R

124

PS2 Interface

OSC NC

SPI Flash ROM

GPIO SM Bus

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A

GPI

1

69

R889 100K_0402_5%

11 24 35 94 113

@ C740 15P_0402_50V8J

Ra

3S/4S# <37> 65W /90W # <37> VLDT_EN <35> LID_SW # <32>

AD_PID0

ECAGND 2

L85

1

R464

C734 C

2

0.1U_0402_16V4Z

Analog Board ID definition +3VALW

EC_SI_SPI_SO <32> EC_SO_SPI_SI <32> 1

Board_ID : 0-> w / X1 1-> wo / X1

EC_SPICS#/FSEL#

R469

L1112 EC_SPICLK <32>Ra <32> FBMA-10-100505-301T_2P C783 10P_0402_50V8J

FSTCHG <37> BATT_BLUE_LED# <32> INT_VGAPW R_ON <24> BATT_AMB_LED# <32> PW R_LED <32> SYSON <35,40,42> Reserve VR_ON <44> ACIN <25,35,37>

BATT_BLUE_LED# INT_VGAPW R_ON BATT_AMB_LED# PW R_LED SYSON VR_ON ACIN

100K_0402_5% AD_BID0

1

R470

Rb

8.2K_0402_5%

2

C735 0.1U_0402_16V4Z

for EMI, close to EC B

EC_RSMRST# <14> EC_LID_OUT# <14> EC_ON <34,38> EC_SW I# <14> BKOFF# <10> W L_OFF# <29> VGA_ON <24,35>

Delay SUSP# 10ms

VGATE <14,44> ENBKL <10> EAPD <27> EC_THERM# <5> SUSP# <35,40,41> PBTN_OUT# <14> EC_PME# <26>

EC_PW ROK_R 1 R254

2 0_0402_5%

EC_PW ROK <14>

C736 4.7U_0603_6.3V6K


20mil

BATT_TEMP

C737 2

100P_0402_50V8J 1

ACIN

C741 2

100P_0402_50V8J 1

A

1

BLM18AG601SN1D_2P


Compal Secret Data 2010/08/20

Issued Date

4

100K_0402_5%

TP_CLK <32> TP_DATA <32>

Deciphered Date

2011/08/20


@

Rb

EC_MUTE# <27>

TP_CLK TP_DATA

2

KB930QF A1 LQFP 128P


32.768KHZ_12.5PF_Q13MC14610002

Project_ID : 0-> 1-> 2->

8.2K_0402_5%

1

AGND

XCLK1 XCLK0 GND GND GND GND GND

4

OSC

X1 @

3

1

NC

1

2

2

C739 @ 15P_0402_50V8J

2 0_0402_5%

+3VALW

DAC_BRIG <10> EN_DFAN1 <34> IREF <37> CALIBRATE# <37>

SPI Device Interface

1

EC_CRY2

2 A

1 R888

Analog Project ID definition

ADP_I <37>

68 70 71 72

2

EC_CRY1

RTC_CLK

BATT_TEMP <39>

ADP_I AD_BID0 AD_PID0

DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F

For Low PWR use <13,17> RTC_CLK

ECAGND 2 1 C731 0.01U_0402_16V7K

R463

DA Output

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

ACOFF <36,37>

BATT_TEMP

2

PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D

ACOFF

1

+5VS

C

EC_SCI#

<14> EC_SCI#

2 1 R462 47K_0402_5% 2 1 C733 0.1U_0402_16V4Z

2

+3VALW

AD

1

BEEP# <27>

2

<13> A_RST#

12 13 37 20 38

BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43

63 64 65 66 75 76

BEEP#

1

LPC_CLK0_EC

<13> LPC_CLK0_EC

PWM Output

21 23 26 27

2

1 33_0402_5%

INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13

1

2 R461

GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC

2

@

1 2 3 4 5 7 8 10

R460

1

C732 @ 22P_0402_50V8J 2 1

<14> EC_GA20 <14> EC_KBRST# <13> SERIRQ <13> LPC_FRAME# <13> LPC_AD3 <13> LPC_AD2 <13> LPC_AD1 <13> LPC_AD0

D

1 100K_0402_5% 1 100K_0402_5% 2 4.7K_0402_5%

2

R459 3S/4S#

EC_GA20 EC_KBRST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

E51RXD_P80CLK <29> E51TXD_P80DATA <29>

+3VALW

VCC VCC VCC VCC VCC VCC

U26

2

1 2 3 4

1 2 3 4

C730

<32>

Place on MiniCard door

JP7

C729 1000P_0402_50V7K

ECAGND

KSO[0..17]

C727

+3VALW

1 2+EC_VCCA BLM18AG601SN1D_2P 1

2

3

2

Title

EC ENE KB930 Size B Date:

Document Number

Rev 1.0

LA-7092P P5WE6/H6/S6 Monday, November 29, 2010

Sheet 1

31

of

47

5

4

3

2

To TP/B Conn. +3VALW

1 R479

C742 1

2 0_0603_5%

2 0.1U_0402_16V4Z

U27

<31> EC_SPICS#/FSEL# +3VALW

EC_SPICS#/FSEL# 2 4.7K_0402_5% SPI_W P# 2 4.7K_0402_5% SPI_HOLD#

R480 1 R482 1

1 3 7 4

CS# WP# HOLD# GND

VCC SCLK SI SO

8 6 5 2

EC_SPICLK_R

+5VS

JTP1

+SPI_VCC

D

1

R481 1

2 0_0402_5% EC_SO_SPI_SI <31> EC_SI_SPI_SO <31>

7 8

EC_SPICLK <31>

1 2 3 4 5 6 GND GND

+5VS

1 2 3 4 5 6

LEFT_BTN# RIGHT_BTN#

C745 0.1U_0402_16V4Z

1 1 C723 C785 100P_0402_50V8J 100P_0402_50V8J 2 2

RIGHT_BTN#

2

4

5 6

4

2

3

TP_DATA

2

RIGHT_BTN#

TP_CLK

LEFT_BTN# D11

2 5 6

LEFT_BTN#

SW 2 SMT1-05-A_4P 3 1

3

SW 1 SMT1-05-A_4P 3 1

D

EMI request For MP


MX25L1605DM2I-12G SOP 8P SA000041N00

TP_CLK <31> TP_DATA <31>

D13

PJDLC05C_SOT23-3

JLED1

C

28 27

A

<31>

ON/OFFBTN# <34>

+3VS

ACES_85201-08051 CONN@

KSO[0..17] <31>

+3VS

R486

5

100K_0402_5%

P G

4

A

Y

1

U29 2

B

3

MEDIA_LED#

5IN1_LED# <29>

1

SATA_LED# <15>


6

PW R_LED#

100P_0402_50V8J

KSO17

C748 1

2

100P_0402_50V8J

C749 1

2

100P_0402_50V8J

KSO7

C750 1

2

100P_0402_50V8J

KSO14

C751 1

2

100P_0402_50V8J

KSO6

C752 1

2

100P_0402_50V8J

KSO13

C753 1

2

100P_0402_50V8J

KSO5

C754 1

2

100P_0402_50V8J

KSO12

C755 1

2

100P_0402_50V8J

KSO4

C756 1

2

100P_0402_50V8J

KSI0

C757 1

2

100P_0402_50V8J

KSO3

C758 1

2

100P_0402_50V8J

KSO11

C759 1

2

100P_0402_50V8J

KSI4

C760 1

2

100P_0402_50V8J

KSO10

C761 1

2

100P_0402_50V8J

KSO2

C762 1

2

100P_0402_50V8J

KSI1

C763 1

2

100P_0402_50V8J

KSO1

C764 1

2

100P_0402_50V8J

KSI2

C765 1

2

100P_0402_50V8J

KSO0

C766 1

2

100P_0402_50V8J

KSO9

C767 1

2

100P_0402_50V8J

KSI5

C768 1

2

100P_0402_50V8J

KSI3

C769 1

2

100P_0402_50V8J

KSI6

C770 1

2

100P_0402_50V8J

KSO8

C771 1

2

100P_0402_50V8J

KSI7

C772 1

2

100P_0402_50V8J

+3VALW

1 R511

LED1 2 750_0402_1% HT-191NB5_BLUE

+3VS

@ 1 R477

2 2 750_0402_1%

B

B

PW R_LED#

1

1

2

2

C747 1

DMN66D0LDW -7_SOT363-6 Q26A

2

<31> PW R_LED KSO16

KSO15

R487 100K_0402_5%

LED2 HT-191UD5_AMBER

1 R478

+3VALW

2 2 3.01K_0402_1%

A

PW R_SUSP_LED#

1

LED3 HT-191NB5_BLUE PW R_SUSP_LED#

3 R490 100K_0402_5%

1 R499

+3VALW

2 2 750_0402_1%

DMN66D0LDW -7_SOT363-6 Q26B

5

<31> PW R_SUSP_LED

2010/08/20

Issued Date

3

1

BATT_BLUE_LED#

BATT_BLUE_LED# <31>

BATT_AMB_LED#

BATT_AMB_LED# <31>

LED4 HT-191UD5_AMBER

1 R498

+3VALW

2 2 3.3K_0402_5%

A

1

For PEW76/86/96 LED light, R477, R499 change as 750 ohm R478 change as 3.01k ohm R498 change as 3.3k ohm

Deciphered Date

2011/08/20


B

Compal Secret Data


5

Pop R486 for RTS5137

2

KSI[0..7]

KSO[0..17]

+3VS

PW R_LED# ON/OFFBTN#

4

ACES_88747-2601 CONN@

KSI[0..7]

+3VALW LID_SW # <31> W LAN_LED# <31>

LID_SW # W LAN_LED# MEDIA_LED#

1

KSO0 G2 KSO1 G1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

2

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

C

1 2 3 4 5 6 7 8 9 10

1

KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7

1 2 3 4 5 6 7 8 GND GND

INT_KBD Conn.

JKB1

B

1

1

PJDLC05C_SOT23-3

2

Title

A

Compal Electronics, Inc. KB/TP/LED/SPI ROM/PWRb

Size B Date:

Document Number

Rev 1.0

LA-7092P P5WE6/H6/S6 W ednesday, November 24, 2010

Sheet 1

32

of

47

A

B

C

D

E

+USB_VCCA

+3VALW

SVPE, 4.2m, 18mohm Change P/N SF000002Y00

+USB_VCCA

1

8 7 6 5

R447 1

9

4.7U_0603_6.3V6K 2

VOUT VOUT VOUT FLG

2

Change 0603 size For DVT C713

GND VIN VIN EN

+ R446 100K_0402_5%

80mil

C712

2 10K_0402_5%

C714 0.1U_0402_16V4Z

AP2301MPG-13_MSOP8

1

C711

2 470P_0402_50V7K

USB_OC0# <14>

1

R448

2

<35> SYSON#

220U_6.3V_M

W=80mils

1

1 2 3 4

EPAD

U24

2

+5VALW

1

1

+USB_VCCA

1

@

2

0_0402_5%

L83 USB20_N0

<14> USB20_N0

1

JUSB1

1

2

2

USB20_P0

1

VOUT VOUT VOUT FLG

8 7 6 5

80mil

R450 100K_0402_5%

3

3

AP2301MPG-13_MSOP8

4

WCM2012F2S-900T04_0805 USB_OC2# <14> R451

1 2 R452 10K_0402_5%

1

@

2

1

2

1 2 3 4 GND GND GND GND

SUYIN_020133MB004S580ZL-C CONN@

0_0402_5%

USB_OC1# <14>

9

4.7U_0603_6.3V6K 2

GND VIN VIN EN

R449 @ 0_0402_5% 1 2

2

Change 0603 size For DVT C715

EPAD

U25

1 2 3 4

1

<14> USB20_P0 +USB_VCCB

4

1 2 3 4 5 6 7 8

USB20_N0_R USB20_P0_R

+3VALW +5VALW

1

C716 0.1U_0402_16V4Z

SYSON#

D10 USB20_N0_R

SA00003XM00 S IC AP2301MPG-13 MSOP 8P PWR SW

4

3

5

2

6

1

USB20_P0_R

2

2

+USB_VCCA

To USB/B Connector

PJUSB208_SOT23-6

Change P/N SC300000O00 for ESD

+USB_VCCB

USB20_N2 USB20_P2

3

USB20_N1 <14> USB20_P1 <14>

S

BT@ 2 1 R453 10K_0402_5%

<31> BT_ON# USB20_N2 <14> USB20_P2 <14>

2

+BT_VCC C721

+BT_VCC


10

9

GND 8 7 6 5 4 3 2 GND 1

8 7 6 5 4 3 2 1

AO3413L_SOT23-3

W=40mils

BT@ 0.1U_0402_16V4Z

JBT1

1U_0402_6.3V4Z 3

C720

2

G D


BT@ Q24

BT@ C719

1

BT@

C722

BT@

1

GND GND

USB20_N1 USB20_P1

BT@ 0.1U_0402_16V4Z

BT@ R454 300_0603_5%

4.7U_0603_6.3V6K 2 0.1U_0402_16V4Z

2

13 14

1

C718

USB20_P7 <14> USB20_N7 <14>

1

3

+3VS

1

1 2 3 4 5 6 7 8 9 10 11 12

1 2 3 4 5 6 7 8 9 10 11 12

+3VALW

Bluetooth Conn.

JUSB2

D

3

(Port 1,2)

S

BT@ Q25 2N7002_SOT23

2 G

ACES_87213-0800G CONN@

4

4

Issued Date


Compal Secret Data


Deciphered Date

2011/08/20

Title


USB/BT/USBsub Rev 1.0


Date:

A

B

C

D


Sheet E

33

of

47

FAN1 Conn

Power Button


+5VS

2 +VCC_FAN1 ON/OFF <31> 51_ON# <36>

2

C824 1000P_0402_50V7K 1 2

R568 10K_0402_5%

1000P_0402_50V7K 1

40mil 2 1

S 2N7002_SOT23

10K_0402_5%

C825 1000P_0402_50V7K

1 2 3

G1 G2

4 5

CONN@ ACES_85204-03001

2

H4 H_3P0

1

1 H12 H_3P0

H3 H_4P0

H19 H_3P0

H24 H_3P0

1

1

H11 H_3P0

H2 H_4P0

1

1

H1 H_3P0

H18 H_3P4

1

H14 H_3P0

2010/08/20

Deciphered Date

H7 H_3P0

H8 H_3P0

H20 H_4P2

H21 H_4P2

H17 H_3P0X3P5N

H10 H_3P0

H22 H_4P2

H23 H_4P2

H13 H_3P0N

1

FD4

1

FD3

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80


Compal Secret Data


FD2

H5 H_3P0

1

FD1

1

3

R496

Q27

2 G

1

2

EC_ON

1

4 6 5

2

<31,38> EC_ON

1 2 3

<31> FAN_SPEED1

1

SMT1-05-A_4P 1 3

JFAN1

+VCC_FAN1

D

1

1

Bottom Side @ SW 4

1

C773

+3VS

0.01U_0402_25V4Z

2

1

6 5

Change to SC600000B00


C823 10U_0603_6.3V6M 1 2

APL5607KI-TRG_SO8

@

DAN202UT106_SC70-3

ON/OFFBTN# <32>

C822

1

4

2 0_0402_5% 1

1

2

1 R567

@ D26 BAS16_SOT23-3 1 2

1

3

<31> EN_DFAN1

8 7 6 5

1

2

GND GND GND GND

1

D12

1

EN VIN VOUT VSET

1

ON/OFFBTN#

1

Bottom Side

@ SW 3 SMT1-05-A_4P 1 3

U37

1 2 3 4

1

100K_0402_5%

2

R495

2 @ 10K_0603_5%

D25 1SS355_SOD323-2

@ R566 0_0603_5% @

1

1

2 @ 10K_0603_5%

+5VS

10U_0603_6.3V6M 2

1

R494

1

2

R493

C821 1

1

+3VALW

TOP Side

1

ON/OFF switch

2011/08/20


Title

Other IO/USB (right) Size Document Number Custom

Rev 1.0


Date: W ednesday, November 24, 2010

Sheet

34

of

47

C

+3VALW TO +3VS

<25,31,37> ACIN


2 2

1

2

3 3 3

S

<24,25> VGA_PWR_ON

S SSM3K7002FU_SC70-3

1

D

S

Q68 2N7002_SOT23

2 G

R1123 100K_0402_5% 2

2

1

VGA_PWR_ON#

<25> VGA_PWR_ON# SUSP 2 G Q65 2N7002_SOT23

1

Q67

2 G

3

R1119 100K_0402_5%

3

C1463 0.1U_0603_25V7K

D 3

1 200K_0402_5% 1

1 +5VALW 2

R1120 470_0603_5%

1

S

R1134 10K_0402_5%


3

1

R1122 2

3

2

2 1 1

Q77 2N7002_SOT23

S

Q62 2N7002_SOT23

R1118 100K_0402_5%

D

2 G

D

2 G

2

2

<13,24> PE_GPIO1

D

SUSP#

PE_GPIO1#

<24> PE_GPIO1#

1

C1461

2

R1117 100K_0402_5%

1

1

R1115 10K_0402_5%

3

1.5_VDDC_PWREN#

+1.5VS

10U_0603_6.3V6M 2

Q59 2N7002_SOT23

+5VALW

<24,43> 1.5_VDDC_PWREN

2 2

G

R1121

S

S

R1131 100K_0402_5%

D

S

1

100K_0402_5%

1

1 1 1

S

0.1U_0603_25V7K

1

D

2 G

+5VALW 2 SUSP G Q60 2N7002_SOT23

C1456

Q63 SI2301CDS-T1-GE3_SOT23-3

3

<31,40,41> SUSP#

D

+1.5VS 3

Q58 2N7002_SOT23

R1113 10K_0402_5%

<25> 1.5_VDDC_PWREN#

+1.5V

D

2 G

1

2

1

R1110 470_0603_5%

SUSP

<42> SUSP

2

S

VGA_ON#

1

1

Q57 2N7002_SOT23

2

D

R1116 100K_0402_5%

R1114 100K_0402_5%

2 1


SUSP

2 Q61 G 2N7002_SOT23

1

10U_0603_6.3V6M C1455 2 2 1U_0402_6.3V4Z

3VS_GATE

1 120K_0402_5%

1

2 R1112

3

+VSB

0.1U_0603_25V7K

2

10U_0603_6.3V6M 2 2 10U_0603_6.3V6M

Audio issue For DVT

C1452

1

+5VALW

1

1

Q52 2N7002_SOT23

1 1

C1454

2

S

+5VALW

C1451

<24,31> VGA_ON

3

1

S

1

D

2 G

R1109 100K_0402_5%

S

R1107 10K_0402_5%

1

U41 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5 4

C1453

D

ACIN 2 G

+3VALW

2

S 2N7002_SOT23

2 VLDT_EN# G Q54

<31,40,42> SYSON

2

S

+3VS


D

Q51 2N7002_SOT23

2 G

2

2 Q56 G 2N7002_SOT23

1

D

VLDT_EN#

R1106

0.1U_0603_25V7K

300K_0402_5%

2 Q55 G 2N7002_SOT23

1.1VS_GATE

<31> VLDT_EN

SYSON#

<33> SYSON# D

1

2 47K_0402_5%

470_0603_5%

1

1 R1105

VLDT_EN#

R1102

2

+VSB

1

C1450

SUSP

1 2

2


3

S

2 10U_0603_6.3V6M

1

1

1

10U_0603_6.3V6M C1449 2 2 1U_0402_6.3V4Z

1

3

1

D

C1447

2

2 SUSP G Q53 2N7002_SOT23

S

1

3

5VS_GATE

2 100K_0402_5%

3

1 R1103

R1104 C1448 1K_0402_5%

D

Change 0603 size For DVT +VSB

1

R1101 470_0603_5%

4

1

R1108 100K_0402_5%

R1111 100K_0402_5%

1

2 1

10U_0603_6.3V6M C1444 2 2 1U_0402_6.3V4Z

3

10U_0603_6.3V6M 2 2 10U_0603_6.3V6M

1

C1446

2

1

1

C1445

+1.1VS

U39 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5


+5VALW


+1.1VALW

1

1

+5VS

4

C1443

+5VALW

+1.1VALW TO +1.1VS


U38 SI4800BDY-T1-GE3_SO8 8 1 7 2 6 3 5


E

1

+5VALW TO +5VS +5VALW

D

3

B

1

A

1

1

D

D

1

D

2 SUSP G Q80 2N7002_SOT23

S

S

2 VLDT_EN# G Q74 2N7002_SOT23

S

3

2 SYSON# G Q78 2N7002_SOT23

3

3

S

3

D

4

1

1

R1126 470_0603_5% VGA@

1

R1128 470_0603_5%

1

R1137 470_0603_5%

2

2

+VGA_CORE

1

R1135 470_0603_5% 4

+1.1VS

2

+0.75VS

2

+1.5V

2 1.5_VDDC_PWREN# G Q28 2N7002_SOT23 VGA@

2010/08/20

Issued Date


Compal Secret Data


2011/08/20

Deciphered Date

Title


DC Interface Rev 1.0


Date:

A

B

C

D


Sheet E

35

of

47

5

4

1

1

1 PC3 100P_0402_50V8J

2

PC2 100P_0402_50V8J

2

2

1 2

PC1 1000P_0402_50V7K

2

VIN

PL1 SMB3025500YA_2P 1 2

1 2 3 4 GND GND

1

@ PJP1 ACES_50305-00441-001

3

PC4 1000P_0402_50V7K

D

D

2

VIN

1

PD2 LL4148_LL34-2 2 1

BATT+

1

1

PD1 LL4148_LL34-2

2 1

<34> 51_ON#

2

VS

1 PJ1 PC6 0.1U_0603_25V7K

+3VALWP

1

1

2

PJ2 2

+3VALW

1

+1.8VSP

1

(4.73A,200mils ,Via NO.= 10)

+1.8VS

C

(3A,120mils ,Via NO.=6)

2 PJ3

PR4 22K_0402_5%

+5VALWP

1

1

2

PJ4 2

+5VALW

1

+1.1VALWP

PreCHG

@

(3.15A,140mils ,Via NO.=7)

1

1

2

PJ6 2

+VSB

1

+0.75VSP

2

2

+0.75VS


(120mA,40mils ,Via NO.= 2)

@PJP3 @ PJP3 JUMP_43X118 1 2 2

1

+VGA_COREP

@PJP4 @ PJP4 JUMP_43X118 1 2 2

1

+VGA_CORE B

1

(13A,520mils ,Via NO.= 26)

1

12

@ PR13 100K_0402_5%

@ PD4 2

PJ11 1

2

+1.05VSP

2

3

3

BAS40CW_SOT323-3

@PQ3 @ PQ3 PDTC115EU_SOT323-3

@ PQ4 PDTC115EU_SOT323-3

1

1

2

+1.05VS

2

JUMP_43X118

PJ7


+1.5VP

1

3

<38> +5VALWP

1

JUMP_43X79

1

@ PR12 1K_1206_5% 1 2

<31,37> ACOFF

+1.1VALW

(5A,200mils ,Via NO.= 10)

B+

2

PR9 1 @ 2

@ PR11 1K_1206_5% 1 2 B

3

PR10 1

1

@ PR8 1K_1206_5% 1 2

100K_0402_5%

2

@PQ2 @ PQ2 TP0610K-T1-E3_SOT23-3

2

+3VLP

@PD3 @ PD3 LL4148_LL34-2

100K_0402_5%

PR7 0_1206_5% 1 2

VIN

2

2

JUMP_43X118

JUMP_43X39 PR5 0_0603_5% 1 2

1

JUMP_43X118

PJ5

+VSBP

+CHGRTC

2

2

JUMP_43X118

JUMP_43X118

2

1

3

PR2 68_1206_5%

2

1 PR3 100K_0402_5%

C

PC5 0.22U_0603_25V7K 2 1

N1

2

PR1 68_1206_5% PQ1 TP0610K-T1-E3_SOT23-3

1

2

+1.5V

2

JUMP_43X118 PJ13 1 1 2 2 JUMP_43X118


PJ16

+1.5VSP

1

1

2

+1.5VS1

2

JUMP_43X118

(1A,40mils ,Via NO.= 2)

A

Compal Secret Data


2010/07/13

2011/07/13

Deciphered Date

Title

A

Compal Electronics, Inc. PWR DCIN / Pre-charge


Rev 0.1

P5WE0 M/B LA-6901P Schematic

Date:

5

4

3

2


Sheet 1

36

of

47

B

C

UGATE

17

DH_CHG

2

PC23 0.1U_0603_25V7K BST_CHGA 2 1

12

15

VADJ

LGATE

14

GND

PGND

13

6251VDDP 2

VDDP

ACLIM

PD8 RB751V-40_SOD323-2

DL_CHG

PC28 4.7U_0603_6.3V6M

2 1

1

@

@

1 2 PR44 15.4K_0402_1%

3

2

<31> CALIBRATE#

PR45 31.6K_0402_1% 6251VDD

CC=0.6~4.48A

IREF=0.43V~3.24V

1

PR48 10K_0402_1% 1 2

PR47 10K_0402_1% 2

PR46 47K_0402_5%

ACIN <25,31,35>

1

PACIN

1

PR49 14.3K_0402_1% 2

ARN

2 PQ19 PDTC115EU_SOT323-3

Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451

4

Compal Secret Data


2010/07/13

Deciphered Date

2011/07/13

Title

Compal Electronics, Inc. PWR-CHARGER


Date:

A

PC253 0.1U_0603_25V7K 2 1

3

2

BATT+

4 PR34 0.02_1206_1% 3

S

Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224

4

1

3

12.60V

PC16 10U_1206_25V6M 2 1

PR41 4.7_0603_5%

2

12600mV

PQ16 AO4466_SO8 4

26251VDD

1

2

11

<40,41>

TCR=50ppm / C PL2 10UH_PCMB104T-100MS_6A_20% CHG 1 2

2

PR37 0_0603_5% BST_CHG 1

1

1 PR43 20K_0402_1%

10

@ PC17 2200P_0402_25V7K

@ PQ12 2N7002W -T/R7_SOT323-3

2

1

16

BOOT

2 G

4

2

CHLIM

S

1

VREF

PQ61 2N7002W -T/R7_SOT323-3 2 PACIN G

PC26 10U_1206_25V6M 2 1

8

S

D

2

PHASE

1

ICM

18

2

19

1

CSIP

VCOMP

PQ15 AO4466_SO8

5 6 7 8

7

2

PC25 10U_1206_25V6M 2 1

6

ARN

3 2 1

2

1

1

CSOP

D

3

20

IREF=0.7224*Icharge Normal 3S LI-ON Cells

PC11 2200P_0402_25V7K 2 1

1 CSIN

CSON

1

ICOMP

2 1 @ PR21 100K_0402_5%

ARN <38>

1

CV mode

PC10 0.1U_0603_25V7K 2 1

2 1

PC14 1000P_0402_25V8J 2 1

2

V1

PR28 20_0402_5% 1 2 PC18 0.047U_0402_16V7K 1 2 PR29 20_0402_5% 2 1 PR30 PC21 20_0402_5% 0.1U_0603_25V7K 1 2 PR32 2_0402_5% LX_CHG

PR31

1

PC15 DCIN 2 1

1

Charging Voltage (0x15)

BATT Type

PQ9 PDTC115EU_SOT323-3

PR35 4.7_1206_5%

PC19 6800P_0402_25V7K 1 2 5

VIN

ISL6251AHAZ-T_QSOP24 3

<31> 65W/90W#

mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A

2

PC27 680P_0402_50V7K

21

6251aclim

D

2 G PQ18 2N7002W -T/R7_SOT323-3

PR357 200K_0402_1% 1 2

5 6 7 8

CSOP

1

ACOFF

2

PD12 1SS355_SOD323-2

3 2 1

CELLS

2

3


1

PC9 10U_1206_25V6M 2 1

1 2 4

0.01U_0402_25V7K 10K_0402_1% 1 2 PR33 100_0402_1% 1 2 6251VREF PC22 .1U_0402_16V7K

12.1K_0402_1%

1

PR23 14.3K_0402_1%

PR40 6251VREF

PR15 10K_0402_1%

ACSETIN

2

2

<31,36> ACOFF

2

PR22 10_1206_5% 2 1 1 CSON

1 2 1 PR42 2.55K_0402_1%

PR39 100K_0402_1% ACOFF

VIN

2

PR26

EN

22

6251_EN

9 PC24 0.01U_0402_25V7K 2 1

<31> IREF

PR36 80.6K_0402_1% 2 1 1

1

PR38 47K_0402_5% 1 2

PR16 47K_0402_1% 2

PD9 1SS355_SOD323-2

@

1

3

4

S <31> ADP_I

3

23

PC20 1 2

5 G

PACIN

24

DCIN

ACSET ARN

1

PQ14B DMN66D0LDW -7_SOT363-6

3

3

D

1

0.1U_0603_25V7K ACSETIN 2

S PQ14A DMN66D0LDW -7_SOT363-6

VDD

2

<31> 3S/4S# 1

2

1

3


2

6 2 G

PD5 RB751V-40_SOD323-2

PU1 1

1

1

PR27 150K_0402_1% PQ10 PDTC115EU_SOT323-3

PR18 191K_0402_1%

6251VDD

PR24 0_0402_5% 2 1

8 7 6 5

CSIN

VIN PreCHG

<31> FSTCHG

2

3

PR25 47K_0402_5% 1 2

6251VDD

D

2

1 2 3

CHG_B+

PL22 HCB4532KF-800T90_1812 1 2

CSIP

47K

PQ8 PDTA144EU_SOT323-3

4

PC13 2.2U_0603_6.3V6K 2 1

PR17 200K_0402_1%

1

V1

1

2

47K 2

PR14 0.02_2512_1%

PC7 5600P_0402_25V7K 1 2

1 3

2

2

PR19 200K_0402_1%

PC12 0.1U_0603_25V7K 2

1

1

1

P3

PQ7 SI4459ADY-T1-GE3_SO8 8 7 6 5

1 2 3

4

1 2 3

4

8 7 6 5

100K_0402_1%

P2

PQ6 AO4407A_SO8

VIN

PL17 1.2UH_1231AS-H-1R2N=P3_2.9A_30% 1 2

B+

4

= 85%*Iada ; = 4.07A

ADP_I = 19.9*Iadapter*Rsense

D

PQ5 AO4407A_SO8

3

@ PC30 10U_1206_25V6M 1 2 @ PC56 10U_1206_25V6M 1 2

PC8 10U_1206_25V6M 2 1

A

Iada=0~4.74A(90W/19V=4.736A)

B

C

Rev 0.1 P5WE0 M/B LA-6901P Schematic

W ednesday, November 24, 2010 D

Sheet

37

of

47

5

4

3

2

1

PC29 1U_0603_10V6K

2VREF_8205

1

1

4

12

LGATE2

LGATE1

19

LG_5V

PL5 4.7UH_PCMC063T-4R7MN_5.5A_20% 1 2

2

RT8205EGQW _W QFN24_4X4

4

1

NC

5 6 7 8

PC38 0.1U_0603_25V7K 2 1

PC37 2200P_0402_50V7K 2 1

LX_5V

18

VIN

VREG5 17

16

GND

SKIPSEL

EN 13

PC36 4.7U_0805_25V6-K 2 1

UG_5V

20

1

LG_3V

3 2 1

2

AO4712_SO8 PQ23

PC46 1U_0603_10V6K 2 1

RT8205_B+

2VREF_8205

S

PC47 4.7U_0805_10V6K

2

1

VL

Typ: 175mA

+5VALWP

1 +

PC43 220U_6.3V_M

2

B

TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP)

1

+3.3VALWP Ipeak=6.768A ; 1.2Ipeak=8.12A; Imax=4.738A f=375KHz, L=4.7UH,Rentrip=162k ohm Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.774A Vlimit=10*10^-6*162Kohm/10=0.162V Ilimit=0.162/(18m*1.2)~0.162/(15m*1.2)=7.5A~9A Io=8.274A~9.774A

+5VALWP Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A f=300KHz, L=4.7UH,Rentrip=154k ohm Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vlimit=10*10^-6*154Kohm/10=0.15V Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A Io=8.44~9.86A

Compal Secret Data


Issued Date

5

21

@ PR60 4.7_1206_5%

PHASE1

@ PC45 680P_0402_50V7K

PHASE2

3 2 1

11

SPOK <39,41>

A

3

PC49 2.2U_0603_6.3V6K

2

1

2

PR66 100K_0402_1%

2

1 3

1

VS

2 1 PR67 40.2K_0402_1%

1

PQ24A DMN66D0LDW -7_SOT363-6



2

D

2 G

3

<31,34> EC_ON

S

2 G

22

UGATE1

VFB=2.0V

1 5

2N7002W -T/R7_SOT323-3 PQ26 <37> ARN

BOOT1

PR57 PC41 0_0603_5% 0.1U_0603_25V7K BST_5V 1 2 1 2

PR64 100K_0402_1% 2 1

VL

A

23

5 6 7 8

LX_3V

PC35 4.7U_0805_25V6-K 2 1

ENTRIP1

UGATE2

2 PC48 0.1U_0603_25V7K

6

3

G S

D

24

1 2

PR62 100K_0402_1%

ENTRIP2

D PQ24B DMN66D0LDW -7_SOT363-6

PR65 200K_0402_5% 2 1

VO1 PGOOD

C

PQ21 AO4466_SO8 4

B+

ENTRIP1

PR63 0_0402_5% 2 1

1

2

3

BOOT2

10

PR61 499K_0402_1% 1 2

B

<39> MAINPWON

ENTRIP1

FB1

REF

4

9

UG_3V

4

1 2 3

FB2

BST_3V

PR59 @ 0_0402_5% 2 1

MAINPW ON

TONSEL

VREG3

15

PQ22 AO4712_SO8

ENTRIP2

VO2

8

14

1 2 3

2 1 2 0_0603_5% PC40 0.1U_0603_25V7K

8 7 6 5

@ PR58 4.7_1206_5% 2 1

2

P PAD

RT8205_B+

PR55 154K_0402_1% 2

7 PR56

+ @ PC44 680P_0402_50V7K 2 1

PC42 220U_6.3V_M

6

1

25

1

5

+3VLP

1

1

PR53 20K_0402_1% 1 2

PU2

4.7UH_PCMC063T-4R7MN_5.5A_20% PL4 1 2

+3VALWP

PR52 20K_0402_1% 1 2

2

PQ20 AO4466_SO8 4

PR51 30K_0402_1% 1 2

PR54 137K_0402_1% 1 2

PC39 4.7U_0805_10V6K

8 7 6 5

PC34 2200P_0402_50V7K 2 1

PC33 4.7U_0805_25V6-K 2 1

C

Typ: 175mA PC32 4.7U_0805_25V6-K 2 1

PC31 0.1U_0603_25V7K 2 1

B+

PL3 HCB4532KF-800T90_1812 1 2

PR50 13K_0402_1% 1 2

ENTRIP2

RT8205_B+

D

2

D

Deciphered Date

2011/07/13


3

2

Title

Compal Electronics, Inc. 3VALWP/5VALWP

Size Document Number Custom

Rev 0.1


Date:

W ednesday, November 24, 2010

Sheet 1

38

of

47

5

4

3

2

1

PJP2 SUYIN_200275GR008G13GZR D

10 9 8 7 6 5 4 3 2 1

2

EC_SMDA EC_SMCA TH PI

PR68 100_0402_1%

PH1 under U botten side : U thermal protection at 92 degree C Recovery at 56 degree C

2

GND GND 8 7 6 5 4 3 2 1

1

D

PR69 100_0402_1%

EC_SMB_DA1 <31>

VL

1

1

<40,41> VMB <40,41> BATT+

PC50 0.1U_0603_25V7K

PR72 21K_0402_1%

VCC TMSNS1 GND RHYST1

8 7

2

6

PR76 9.53K_0402_1%

1

2 3

2

<38> MAINPWON

4 BATT_TEMP <31>

OT1 TMSNS2 OT2 RHYST2

2

1

PU3 1

5

2

C

1

@ PR77 47K_0402_1% 1

G718TM1U_SOT23-8

1

1

1

@ PR74 100K_0402_1% PR75 1K_0402_1%

C

1

PR71 10K_0402_1%

VL

+3VALWP 2

PC52 0.01U_0402_25V7K

2

1 PR73 6.49K_0402_1% 2 1

1 PC51 1000P_0402_50V7K

2

2

1

2

EC_SMB_CK1 <31> PR70 1K_0402_5%

2

PL6 SMB3025500YA_2P 1 2

PH2 @

PH1

2

100K_0402_1%_N15WF104F03RC 2

100K_0402_1%_N15WF104F03RC PQ28 TP0610K-T1-E3_SOT23-3

3

2

1

+VSBP

PC54 0.1U_0603_25V7K

2

1 2

1

2

VL

PC53 0.22U_0603_25V7K

PR79 22K_0402_1% 1 2

2 1 PR78 100K_0402_1%

B+

PR80 100K_0402_1% 1

1 2

D

S

PQ29 2N7002W-T/R7_SOT323-3

2 G PC55 1U_0402_6.3V6K

<38,41> SPOK

PR81 1K_0402_5% 1 2

3

B

1

B

A

A

Compal Secret Data


2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc. PWR-BATTERY CONN/OTP


Rev 0.1


Date:

5

4

3

2


Sheet 1

39

of

47

B

C

FB

6

0.22U_0402_10V6K

FB_1.8VS

PR85 10K_0402_1%

1

2

2

1M_0402_5%

PR83 20K_0402_1%

2

1 1 PC120

PR86

PC119

1

1

LX_1.8VS

200K_0402_5% @

2

NC

NC

1

TP

2 EN_1.8VS

7

11

PR84

PR82

1 2 1

<31,35,41> SUSP#

FB=0.6Volt

PC118 22U_0805_6.3VAM

1

1

EN

PC115 22U_0805_6.3VAM

+1.8VSP

2

SVIN

5

3

PC117 22U_0805_6.3VAM

8

LX

LX_1.8VS

PC116 68P_0402_50V8J 2 1

PVIN

2

1

9

JUMP_43X39

LX

2

PVIN

1

10

2

1

4.7_1206_5%

1

680P_0603_50V7K

1

2

2

2

+5VALW

D

PL7 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% 1 2

4

PU4 SY8033BDBC_DFN10_3X3 @ PJ14

PG

A

G5603

RT8209B

℃

Temperature Compensated

TPS51117

℃

-1180ppm/

RT8209M

℃

℃

1600ppm/

4500ppm/

4800ppm/

50mV

30mV

50mV

2

2

PR87 255K_0402_1% 1 2 2 1

2

5

FB

6

PGOOD

15 NC

14 UGATE

13

DH_1.5V

PHASE

12

LX_1.5V

CS

11

VDDP

10

LGATE

9

VFB=0.75V

3 2 1

PL9 1.0UH_PCMC104T-1R0MN_20A_20% 2

1

+1.5VP

0.1U_0603_25V7K

PR92 1 2 7.68K_0402_1%

@ PR93 4.7_1206_5%

+5VALW

1

DL_1.5V

+ PC128 330U_6.3V_M

4

3

2

2

PGND

RT8209MGQW _W QFN14_3P5X3P5

PC131 4.7U_0805_10V6K

PQ31 AO4726L_SO8

@ PC130 680P_0603_50V7K

2

8

7

2

GND

PC129 4.7U_0603_6.3V6K

3

PQ30 AO4466_SO8

PC127 1 2

5 6 7 8

VDD

BST_1.5V-1

BOOT

VOUT

4

0_0603_5%

1

100_0603_5%

3

2

2

PR91

TON

4

PR89

1

1

+5VALW

2

1

PU5

EN/DEM

PC126 @ .1U_0402_16V7K

2

2

PR90 30K_0402_5%

1

3 2 1

0_0402_5%

BST_1.5V

1

PR88

1

1

<31,35,42> SYSON

B+

PC125 2200P_0402_50V7K 2 1

200mV

PC124 0.1U_0603_25V7K 2 1

200mV

PC123 4.7U_0805_25V6-K 2 1

200mV

PC121 4.7U_0805_25V6-K 2 1

200mV

PL8 HCB2012KF-121T50_0805 1 2

5 6 7 8

Vtrip_max (SPEC)

30mV

1

Vtrip_min (SPEC)

Rtrip: 5KΩ~15KΩ Rds(on) = 5.3m ohm (typ) 7m ohm (max) 1

PR94

2

1

5.1K_0402_1%

2

PR95 5.1K_0402_1%

VFB=0.75V Vo=0.75*(1+10K/10K)=1.5V Fsw=280KHz

4

Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm Ipeak=9.45A, Imax=6.615A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A =>1/2Delta I=2.467A Vtrip=Rtrip*10uA=0.0768 Iomin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A Iomax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A Io=11.61A~14.54A

4

Issued Date


Compal Secret Data


Deciphered Date

2009/04/28

Title


Date:

A

B

C

1.8VSP/1.5VP Rev 0.1


Sheet

40

of

47

A

B

C

D

PL10 HCB2012KF-121T50_0805

PR96 255K_0402_1% 1 2

PR97 0_0402_5% 1 2

PC208 0.1U_0603_25V7K

PC207 0.1U_0603_25V7K 2 1

PC135 2200P_0402_50V7K 2 1

1

PC134 0.1U_0603_25V7K 2 1

2

1 2

1

PR98 0_0603_5% 1 2

PQ32 AO4466_SO8

LGATE

9

DL_1.1VALW

2

PQ33 AO4712_SO8

4 1

PGND 8

GND 7

2

PC139 4.7U_0603_6.3V6K

+5VALW


PC140 4.7U_0805_10V6K

Rtrip: 5KΩ~15KΩ

PR103 4.7K_0402_1% 1 2

PC138 330U_6.3V_M

10

1

VDDP

2 PR102 10.7K_0402_1%

LX_1.1VALW 1

@ PR100 4.7_1206_5%

11

1

PGOOD

12

CS

2

6

PHASE

@ PC141 680P_0603_50V7K

FB

13

5 6 7 8

5

DH_1.1VALW 0.1U_0603_25V7K

UGATE

3 2 1

VDD

BOOT

VOUT

4

14

15

1

3

2

2

PR101 100_0603_1% 1 2

TON

PL11 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 1 2

PC137 1

1

+5VALW

2

NC

2

PU6

EN/DEM

1

PC136 .1U_0402_16V7K @

2

PR99 30K_0402_5% @

BST_1.1V ALW

B+

VFB=0.75V V=0.75*(1+4.7K/10K)=1.1V Fsw=280KHz

1

Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm Ipeak=4.5A, Imax=3.15A Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=1.68A =>1/2Delta I=0.84A Vtrip=Rtrip*10uA=0.107 Iomin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=5.79A Iomax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=6.78A Io=5.79A~6.78A

1

<38,39> SPOK

2

4

3 2 1

1

PC133 4.7U_0805_25V6-K

2

5 6 7 8

1

PC132 4.7U_0805_25V6-K

1.1VALW _B+

+1.1VALW P

1 + 2

2

1

2

PR104 10K_0402_1% 2

PL12 HCB2012KF-121T50_0805

3 2 1

CS

11

VDDP

10

PR111 8.25K_0402_1%

9

DL_1.05VALW

LX_1.05VALW

7

LGATE

2

4


2

PC150 4.7U_0805_10V6K

Rtrip: 5KΩ~15KΩ

PR112 4.02K_0402_1% 1 2 1

RT8209B

Vtrip_min (SPEC)

℃

-1180ppm/

30mV

℃

TPS51117

RT8209M

℃

℃

1600ppm/

4500ppm/

4800ppm/

50mV

30mV

50mV

200mV

200mV

200mV

200mV

2010/01/25

Deciphered Date

PC206 0.1U_0603_25V7K

2009/04/28

Title


Date:

A

B

C

4


Compal Secret Data


Vtrip_max (SPEC)

PC205 0.1U_0603_25V7K 2 1

PC145 2200P_0402_50V7K 2 1

PC144 0.1U_0603_25V7K 2 1

1 2

PC143 4.7U_0805_25V6-K 2 1

2

G5603

+ 2


4

Temperature Compensated

1

VFB=0.75V V=0.75*(1+4.02K/10K)=1.05V Fsw=280KHz

Rds(on) = 5.3m ohm (typ) 7m ohm (max)

PR113 10K_0402_1%

+1.05VSP

3

PQ35 AO4726L_SO8

1

PGND 8

PGOOD

GND

6 2

PC149 4.7U_0603_6.3V6K

+5VALW

2

1

1

PC148 330U_6.3V_M

12

1

PHASE

PR109 4.7_1206_5%

14

13

PC151 680P_0603_50V7K

FB

PL13 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 1 2

2

DH_1.05VALW 0.1U_0603_25V7K

UGATE

1

VDD

5

1

5 6 7 8

VOUT

4

BST_1.05V ALW PC147

BOOT

3

B+

PQ34 AO4466_SO8

3 2 1

PR110 100_0603_1% 1 2

+5VALW

TON

1

4 PR107 0_0603_5% 1 2

2

3

2

NC

2

PU7

EN/DEM

PC146 .1U_0402_16V7K

2

PR108 30K_0402_5% @

1

1

<31,35,40> SUSP#

1

PR106 200K_0402_5% 1 2

15

PR105 255K_0402_1% 1 2

PC142 4.7U_0805_25V6-K

2

5 6 7 8

1

1.05VALW _B+ 2

1.1VALWP/1.05VSP Rev 0.1


Sheet

41

of

47

14

PGOOD

10

3 2 1

@ PR182 4.7_1206_5%

+5VALW

DL_1.5V-2

9

+1.5VSP

1 +

4

@ PC202 330U_6.3V_M

RT8209MGQW_WQFN14_3P5X3P5

2

@ PQ39 AO4726L_SO8

@ PC200 4.7U_0805_10V6K

@ PC195 680P_0603_50V7K

2

7

LGATE

11

1

2

VDDP

LX_1.5V-2 @ PR185 1 2 7.68K_0402_1%

12

5 6 7 8

15

BOOT

CS

VFB=0.75V

FB

2

6

PHASE

1

1

5

VDD

2

0.1U_0603_25V7K

DH_1.5V-2

3 2 1

100_0603_5%

VOUT

@ PL21 1.0UH_PCMC104T-1R0MN_20A_20%

2

4

13

@ PQ46 AO4466_SO8

@ PC199 1 2

BST_1.5V-2

1

@ PR178 1 2

@ PC196 4.7U_0603_6.3V6K

D

0_0603_5%

UGATE

PGND

3

+5VALW

TON

8

2

NC

PU11

1

@

EN/DEM

@ PC203 .1U_0402_16V7K

2

2

@ PR183 30K_0402_5%

@

4

@ PR181 BST_1.5V-2 1 2

1

0_0402_5%

@

B+

1

@ PR186 1 2

GND

<31,35,40> SYSON

1

D

@

1

@ PL20 HCB2012KF-121T50_0805 1 2

PC197 2200P_0402_50V7K 2 1

@ @ PR180 255K_0402_1% 1 2

PC201 0.1U_0603_25V7K 2 1

2

PC204 4.7U_0805_25V6-K 2 1

3

PC198 4.7U_0805_25V6-K 2 1

4

5 6 7 8

5

Rtrip: 5KΩ~15KΩ

1

@

PR184 2

1

5.1K_0402_1%

VFB=0.75V Vo=0.75*(1+10K/10K)=1.5V Fsw=280KHz

C

@ PR179 5.1K_0402_1%

RT8209B

TPS51117

RT8209M

C

2

G5603 Temperature Compensated

-1180ppm/

℃

1600ppm/

℃

4500ppm/

℃

4800ppm/

Vtrip_min (SPEC)

30mV

50mV

30mV

50mV

Vtrip_max (SPEC)

200mV

200mV

200mV

200mV

℃


PJ15 JUMP_43X39

2

2

1

1

+1.5V

PU8 VIN

NC

8

2

GND

NC

7

3

VREF VCNTL

6

PC153 1U_0603_10V6K

2

PR114 1K_0402_1%

B

+3VALW 1

1

4

VOUT

2

1

PC152 4.7U_0805_6.3V6K

1

2

B

NC TP

5 9

2

1

+0.75VSP

2

S PQ36 2N7002W-T/R7_SOT323-3

PC154 .1U_0402_16V7K 2 1

1 PR116 1K_0402_1%

PC155 10U_0603_6.3V6M

2

PC156 .1U_0402_16V7K

D

2 G 3

PR115 300K_0402_5% 1 2 1

<35> SUSP

1

APL5336KAI-TRL_SOP8P8

For shortage changed

A

A

Compal Secret Data


Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc. 0.75VSP Document Number

Rev 0.3


Sheet 1

42

of

47

5

4

3

2

1

VGA@ PL14 HCB2012KF-121T50_0805

B+

1

B+_CORE

2

1

5

<13,24> VGA_PWRGD

2

TRIP

DRVH

9

DH_VCORE

3

EN

SW

8

SW_VCORE

4

VFB

V5IN

7

5

RF

DRVL

6

1

VGA@ PC162 1U_0603_6.3V6M

1

1

@ PR122 4.7_1206_5%

2

2 4

VGA@ PC163 390U_2.5V_M

+

VGA@ PR124 0_0402_5%

@ PC164 680P_0603_50V7K

VGA@ PR125 10_0402_5% 2 1 GCORE_SEN

GCORE_SEN <21> C

2

3 2 1

VGA@ PQ38 TPCA8057-H_PPAK56-8-5

VGA@ PR126 2.87K_0402_1%

Rds=2.6m/3.2mOHM 1

VGA@ PC165 .1U_0402_16V7K

ESR=10mohm

1

DL_VCORE

11

Switch Freq. (RF pin setting) 47K =>450KHz 100K =>390KHz 200K =>350KHz 470K =>290KHz

+VGA_COREP

2

TP

VFB=0.7V

1 2

C

VGA@ PL15 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 2 +5VALW

TPS51218DSCR_SON10_3X3

<24,35> 1.5_VDDC_PWREN

VGA@ PQ37 TPCA8065-H_PPAK56-8-5

1

2

VGA@ PR120 200K_0402_1%

10

2

2

1 @ PR121 10K_0402_5%

VBST

VGA@ PR118 VGA@ PC161 0_0603_5% 0.1U_0603_25V7K BST_VCORE 1 2 1 2

5

+3VS

VGA@ PU9 1 PGOOD

3 2 1

4

VGA@ PR119 44.2K_0402_1% 1 2

VGA@ PR123 20K_0402_1% 1 2

D

2

VGA@

1

VGA@

@ PR117 10K_0402_5%

2

VGA@

PC160 10U_0805_25V6K 2 1

VGA@

PC159 10U_0805_25V6K 2 1

D

PC158 0.1U_0603_25V7K 2 1

PC157 2200P_0402_25V7K 2 1

+3VS

1

2

+3VSG

1

VGA@ PC167 4700P_0402_25V7K

@ PR132 10K_0402_5%

1

2

1

S

1

3

G

5

DMN66D0LDW-7_SOT363-6 VGA@ PQ40A

2 1

G

2

2

D

VGA@ PR133 10K_0402_5% VGA@ PR134 10K_0402_5% 1 2

VGA@ PR130 40.2K_0402_1% 1 2

6

+3VSG

D

2 VGA@ PR129 10K_0402_5%

1

VGA@ PR128 9.31K_0402_1%

2

VGA@ PC166 2200P_0402_25V7K

2

Ipeak=18.2A Imax=12.74A, 1.2*Ipeak=21.84A Delta I= ((19-0.9)*(0.9/19))/(L*Fsw)=6.8A Iomax=(66.5K*11uA)/(8*1.2*0.0026) +3.4=32.71A Iomin=(66.5K*9uA)/(8*1.2*0.0032)+3.4=22.88A Io=22.88~32.71A

VGA@ PR127 15.4K_0402_1%

1

VGA@ PR131 30.1K_0402_1%

2

1

VGA_CORE Vtrip= 0.7V Vo=0.7*(1+Rtop/Rdown) Fsw=350KHz

B

VGA@ PC168 4700P_0402_25V7K

@ PR135 10K_0402_5%

+3VSG

GPIO 15

GPIO 20

GPU_VID0

GPU_VID1 Core Voltage Level

Seymour

G

VGA@ PQ41B DMN66D0LDW-7_SOT363-6

VGA@ PR140 10K_0402_5% 5 2 1

@ PR139 10K_0402_5%

+3VSG

GPU_VID0 <19>

2

D

11

3

2

2

2

1

S

4

VGA@ PQ40B DMN66D0LDW-7_SOT363-6

1

B

VGA@ PR141 10K_0402_5%

@ PR136 10K_0402_5%

0.9V

D AP

0

1

1.00V 1.05V

0

0

1.10V

GPU_VID1 <19> VGA@ PR138 10K_0402_5%

S

2

0

VGA@ PR137 10K_0402_5% 2 1

1

1

G

VGA@PQ41A DMN66D0LDW-7_SOT363-6

2

1

1

6

1

1

2

4

S

A

A

Compal Secret Data


2010/07/13

2011/07/13

Deciphered Date

Title

Compal Electronics, Inc. +VGA_COREP


Date:

5

4

3

2

Rev 0.1

P5WE6/S6/H6


Sheet 1

43

of

47

B

C

D

E

PL16 HCB2012KF-121T50_0805

U_B+

7 8

ENABLE

LGATE0

ISL6265CHRTZ-T_TQFN48_6X6

RBIAS

PVCC

OCSET

LGATE1

VDIFF0

PGND1

PHASE0

32

+5VALW

28

<5> APU_VDD0_RUN_FB_L 2

PR170 10_0402_1% 1

PC57 10U_1206_25V6M 2 1

PC175 220U_25V_M

PC173 0.1U_0603_25V7K 2 1 2 1

PC212 0.1U_0603_25V7K 2 1

PC211 0.1U_0603_25V7K 2 1

PC210 0.1U_0603_25V7K 2 1

PC209 0.1U_0603_25V7K 2 1

PC214 0.1U_0603_25V7K 2 1

PC185 0.1U_0603_25V7K 2 1

PC184 4.7U_0805_25V6-K 2 1

PC183 4.7U_0805_25V6-K 2 1

PQ45 TPCA8057-H 1N PPAK56-8

PR162 12.7K_0402_1%

PC188 680P_0603_50V7K

PC189 2 1 0.1U_0603_16V7K

PC190 1U_0603_16V6K

2 LGATE0

27

1

PR166 4.53K_0402_1%

26

TP

25

49

ISN1 24

ISP1 23

VW1 22

COMP1 21

FB1 20

VDIFF1 19

VSEN1 18

RTN1 17

16

+APU_CORE

ISN0

VSEN0

0_0402_5% PR171 1 RTN0

2

+1.5V

DIFF_0

2

1

PR169 0_0402_5% 2 1

<5> APU_VDD0_RUN_FB_H

14

PR168 0_0402_5%

1

10_0402_1%

ISP0

2

+APU_CORE

BOOT1

4

30 29

1

3

3

ISP0 ISN0

VSEN1

PR167

13

VSEN1 2

3

RTN0

UGATE1

VW0

VSEN0

COMP0

ISP0

12

PHASE1

15

11

FB0

ISN0

10

3 2 1

PR161 4.7_1206_5%

LGATE0

31

4

2

PGND0

UGATE0

33

PQ44, PQ45 need to link 1

SVC

34

2

PC187 0.22U_0603_10V7K

5

38

39

40

41

37 UGATE_NB

PHASE_NB

LGATE_NB

PGND_NB

43

44

45

42 RTN_NB

VSEN_NB

FSET_NB

46 FB_NB

PHASE0

BOOT0

2

9

UGATE0

SVD

35

2

ISN0

6

PWROK

36

PL19

1

PR163 0_0402_5%

PR165 95.3K_0402_1% 2 1

5

BOOT0

DCR = 1.1m ohm +-7%

0.36UH_PCMC104T-R36MN1R17_30A_20%

ISP0

1

BOOT_NB

PGOOD

BOOT_NB

PR158 2.2_0603_1% BOOT0 1 2 1

PQ44 TPCA8065-H_PPAK56-8-5

1 2

4

ESR = 15 m ohm

PC179 220U_6.3V_M

2

<31> VR_ON PR164 21.5K_0402_1% 2 1

1 PR160 0_0402_5%2

3

2

PHASE0

3 2 1

ISL6265_PWROK

<5> APU_SVD <5> APU_SVC

OFS/VFIXEN

OCSET_NB

2

COMP_NB

VCC

47

VIN

48

1 2

PU10

1

<13> H_PWRGD_L

+

U_B+

PR190 0_0603_5% 1 2 UGATE0-1 4

UGATE0 @ PR156 105K_0402_1%

2 @ PR159 100K_0402_5% 2 PR157 100K_0402_5%

2

Rds(on) max =18 m ohm typ = 15 m ohm

UGATE_NB

2 1

PC180 680P_0603_50V7K

PC182 4.7U_0805_25V6-K 2 1

2

2

1

1 2 1

1

LGATE_NB

@ PR153 105K_0402_1%

1

<14,31> VGATE <14> FCH_PWRGD

PR146 4.7_1206_5%

PC213 0.1U_0603_25V7K 2 1

1 2 PR187 1 10_0402_5%PHASE_NB

@ PR155 10K_0402_1%

2

+APU_CORE_NB

1

<5>

1 2

PQ43 AO4712_SO8

PHASE_NB

PR154 105K_0402_1%

PC174 2200P_0402_50V7K 2 1

5 6 7 8 2

PC186 2200P_0402_50V7K 2 1

1

1

PR152 0_0402_5%

1

PL18 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 1 2

PC178 0.22U_0603_10V7K 4

APU_VDDNB_RUN_FB_H

+ 2

B+

APU_VDD0_RUN_FB_L

PR151 23.7K_0402_1% 2

2

PC181 0.1U_0603_25V7K

LGATE_NB

1

2

PR148 2_0603_5%

+3VS

PQ42 AO4466_SO8

5

+5VS

PHASE_NB PR145 2.2_0603_1% BOOT_NB 1 2 1

PR149 0_0402_5% 2 1 PR150 0_0402_5% 2 1

1

+3VS

UGATE_NB1 4

PC170 1000P_0402_50V7K

PR147 10_0402_5% 1 2 +APU_CORE_NB

2

PR189 0_0603_5% 1 2

PR188 220_0402_1%

1

3 2 1

1

UGATE_NB

PR144 22K_0402_1% 2 1

2

PC177 0.1U_0603_16V7K

U_B+

1

PC176 1000P_0402_50V7K 2 1 1

+5VALW

2

3 2 1

PR142 44.2K_0402_1% PR143 2_0603_5% 1 2

1

PC171 4.7U_0805_25V6-K 2 1

1

5 6 7 8

2

PC172 4.7U_0805_25V6-K 2 1

2 PC169 47P_0402_50V8J 2 1

PC58 10U_1206_25V6M 2 1

A

1K_0402_5% PR172 1

2

VW0

PR173 PC191 255_0402_1% 2200P_0402_25V7K 2 1 2 1

2

1

COMP0

PC192 220P_0402_50V8J

4

PR174 1K_0402_5% 2 1

PR175 2

1

PC194 2 1

2

1

PC193 1000P_0402_50V7K

4

PR176 6.81K_0402_1% 2 1

54.9K_0402_1% 1200P_0402_50V7K

Compal Secret Data

1

Security Classification PR177 36.5K_0402_1%

2009/10/02

Issued Date

2010/10/02

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

@

Date:

A

B

C

D

Compal Electronics, Inc. U_CORE Document Number

Rev 0.3


Sheet E

44

of

47

5

4

3

2

Version change list (P.I.R. List) Item

D

Fixed Issue

1

Page 1 of 1 for PWR Reason for change

Rev.

PG#

Modify List

Date

Change PR115 from SD028000080 to SD028300380(S RES 1/16W 300K +-5% 0402) Add PC156 SE076104K80(S CER CAP .1U 16V K X7R 0402)

Phase

2010/09/24

DVT

1

0.75VSP EN RC value

HW adjust timing

0.1

42

2

1.8VSP EN RC value

HW adjust timing

0.1

40

Change PR84 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402) Add PC120 SE095224K00(S CER CAP 0.22U 10V K X5R 0402)

2010/09/24

DVT

1.05VSP EN RC value

HW adjust timing

0.1

41

Change PR106 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402) Add PC146 SE076104K80(S CER CAP .1U 16V K X7R 0402)

2010/09/24

DVT

HW adjust timing

0.1

43

Change PR123 from SD034100280 to SD034200280(S RES 1/16W 20K +-1% 0402)

2010/09/24

DVT

42

Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185, PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure to VGA@ del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)

2010/10/05

DVT

D

3 4 5

VGA_COREP EN RC value

change BOM structure

1.5VSP change BOM structure to VGA@ for cost down of UMA

0.1

C

C

6

Adjust APU_CORE_NB O to 15A

0.1

44

Add input choke in charger circuit.

Add input choke for EMI ISN test in charger circuit.

0.1

37

8

Add snubber

Add snubber in APU_COREP and APU_CORE_NB circuit.

0.1

44

Add PR146, PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC180, PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PR188 SD034220080(S RES 1/16W 220 +-1% 0402)

9

Add snubber and input Cup.

0.1

41

10

Add input Cup.

0.1

7

Adjust APU_CORE_NB O

Add snubber and input Cup. in 1.05VSP circuit.

Add input Cup. in 1.1VALWP circuit for EMI test.

2010/10/07

DVT

2010/10/18

DVT

2010/10/18

DVT

Add PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PC205, PC206 SE042104K80(S CER CAP .1U 25V K X7R 0603)

2010/10/18

DVT

41

Add PC207, PC208 SE042104K80(S CER CAP .1U 25V K X7R 0603)

2010/10/18

DVT

Add PC209, PC210, PC211, PC212 SE042104K80(S CER CAP .1U 25V K X7R 0603) Add PC57, PC58 SE142106M80(S CER CAP 10U 25V M X5R 1206 H1.7) Add PR189, PR190 SD013000080(S RES 1/10W 0 +-5% 0603)

Change PR151 from SD034110280 to SD034237280(S RES 1/16W 23.7K +-1% 0402)

Change PL17 from SM010018710 to SH00000IY00(S COIL 1.2UH +-30% 1231AS-H-1R2N=P3 2.9A)

B

B

11

Add input Cup.

Add input Cup. and H/S gate resistance in U_COREP circuit for EMI ISN test.

0.1

44

2010/10/19

DVT

12

Adjust VGA_COREP VID value

Adjust VGA_COREP VID value

0.1

43

Change PR128 from SD034100280 to SD034931180(S RES 1/16W 9.31K +-1% 0402) Change PR127 from SD034200280 to SD034154280(S RES 1/16W 15.4K +-1% 0402) Change PR131 from SD000009K00 to SD034301280(S RES 1/16W 30.1K +-1% 0402)

2010/10/21

DVT

13

change BOM structure

1.5VSP change BOM structure to @ for cost down

0.1

42

Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185, PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure to @ del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805)

2010/10/21

DVT

14

change main source

change main source for reduce source

0.1

42

2010/10/26

DVT

Adjust VGA_COREP VID timing to avoid OVP.

0.1

43

2010/11/01

DVT

2010/11/01

DVT

15

Adjust VGA_COREP VID timing

16

Delete precharge circuit

Change PQ36 from SB000009610 to SB000006800(S TR 2N7002W T/R7 1N SOT-323)

Change PR130 from SD028100280 to SD034402280(S RES 1/16W 40.2K +-1% 0402)

A

Delete precharge circuit to avoid adapter UVP.

0.1

36

del PR8, PR11, PR12 SD001100180(S RES 1/4W 1K +-5% 1206) del PD3 SC100001Y80(S DIO LL4148 LL-34 PANJIT) del PR9, PR10, PR13 SD028100380(S RES 1/16W 100K +-5% 0402) change PR7 SD001100180 to SD011000080(S RES 1/4W 0 +-5% 1206)


Compal Secret Data


Issued Date

A

Deciphered Date

2010/10/12

Title


Date:

5

4

3

2

PIR (PWR) Rev 0.1

PEW96 LA-6552P


Sheet 1

45

of

47

5

4

3

2

Version change list (P.I.R. List) Item

D

Fixed Issue

Page 1 of 1 for PWR Reason for change

Rev.

PG#

1

Delete precharge circuit

2

Delete precharge

連連 circuit

Delete precharge

連連 circuit

Delete precharge

連連 circuit to avoid adapter UVP.

0.1

37

4

Delete precharge

連連 circuit

Delete precharge


0.1

37

5

Delete precharge

連連 circuit

Delete precharge


0.1

37

0.1

44

3

1

Delete precharge circuit to avoid adapter UVP.

Delete precharge

0.1


36

0.1

37

Modify List

Date

del PQ2 SB906100210(S TR TP0610K-T1-E3 1P SOT23) del PQ3, PQ4 SB301150200(S TR PDTC115EU NPN SOT323) del PD4 SCS00001200(S SCH DIO BAS40CW SOT-323)

change PQ7 SB00000DL00 to SB00000I600(S TR SI4459ADY-T1-GE3 1P SO8)

del PR21 SD034100380(S RES 1/16W 100K +-1% 0402) del PC17 SE075222K80(S CER CAP 2200P 25V K X7R 0402) del PQ12 SB000006800(S TR 2N7002W T/R7 1N SOT-323)

Phase

2010/11/01

DVT

2010/11/01

D

DVT

2010/11/01

DVT

Add PR357 SD034200380(S RES 1/16W 200K +-1% 0402) add PC253 SE042104K80(S CER CAP .1U 25V K X7R 0603) add PQ61 SB000006800(S TR 2N7002W T/R7 1N SOT-323)

2010/11/01

DVT

Add PD9, PD12 SC100001K00(S DIO 1SS355 SOD323 T/R-5K)

2010/11/01

DVT

C

C

Add PC213, PC214 SE042104K80(S CER CAP .1U 25V K X7R 0603)

6

Add input Cup.

Add input Cup.

in U_COREP circuit for EMI ISN test.

PVT

2010/11/12

7

8 9 10 B

B

11 12 13 14 15 A

A

16

2010/04/12

Issued Date


Compal Secret Data


Deciphered Date

2010/10/12

Title


Date:

5

4

3

2

PIR (PWR) Rev 0.1

PEW96 LA-6552P


Sheet 1

46

of

47

5

PHASE

PAGE

0.1

P08

0.2 0.2 D

0.2

P-P--

4

3

2

1

Modification list

PURPOSE

First release

Base on PEW96, change platform (NB,U-->APU,SB820-->FCH)

C220, C336, C347, C357, C359, C360, C387, C388, C389, C390, C391, C392, C393, C421,

Follow Standard Part 0805-->0603

C427, C428, C1461 change 0603 size C721 C669, C1005, C705, C708, C713, C715, C736, C794, C797, C932, C934, C983


change 0603 size C215, C216, C218, C224, C226, C227, C229, C230, C231, C660, C671, C821, C823,

D

P--

C1210, C1517, C1522, C1526, C1529, C1532, C1512, C1523, C1443, C1445, C1446, C1447,


C1448, C1452, C1453, C1454 change 0603 size

C

0.2

P35

R1122 change as 200k ohm, C1463 change as 0.1UF

Adjust sequence

0.2

P5

Add R109, R155

Pull up 4.7k ohm for CRT EDIE

0.2

P16

Unpop R632, C744, C69, C746; Pop R633

+VDDIO_18_FC Tie to GND for Nun-share ROM

0.2

P16

Add R635; Unpop R634

AMD suggestion for +VDDIO_AZ

0.2

P24

Add R170, R171

For DISO BOM option

0.2

P13

Add U33, C1199, R830, R838, R839

For VGA_PWRGD

0.2

P13

Remove C52, R557

For A_RST#

0.2

P27

EC_MUTE# change as 12 PIN form 46 PIN in Codec

For External Mute Fail issue

0.2

P16

C113, C77, C743, C96 change 0603 size and add C121, C105, C108, C109

22uF cap. change two 10uF cap. 0603 size

0.2

P19

C14 change 0603 size and add C52

22uF cap. change two 10uF cap. 0603 size

0.2

P13

C66, C67 change 27pF

Follow suggestion by TXC result

0.2

P26

C1485, C1486 change 33pF

Follow suggestion by TXC result

0.2

P33

C711 Change as SF000003I00

Material shortage

0.2

P9

Add C643, C675, C676, C678

For DDR3 moat issue

C

0.2

P26

Remove C939 ; Reserve C941, D48, D49, D51, L109

For LAN

0.2

P7

Add C604, C684

For CRT Moniter issue

0.3

P--

C212, C623 change 0603 size ; add C628, C685


0.3

P27

R786 change as 15k ohm

Dos Beep issue

0.3

P19

change R21, R22 as DISO@

Device Menage Audio issue

1.0

P27

Add R797, R800

Mic noise issue

1.0

P26,10

1.0

P32

Reverse C939, C942, R456, R419, R426

for EMI ISN solution

Add C753, C785

for EMI request

B

B

A

A

Compal Secret Data


Issued Date

Change footprint 20100812 5

Deciphered Date

2011/08/20


: For cost down purpose to change parts 4

3

2

Title

Compal Electronics, Inc. HW-PIR

Size B Date:

Document Number

Rev 1.0

LA-7092P P5WE6/H6/S6 Tuesday, November 16, 2010

Sheet 1

47

of

47

Aspire 5253 (compal La-7092p Rev.1.0) 5l4u6f

Overview 5o1f4z

More details 6z3438

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